CS250, UC Berkeley Fall ‘11Lecture 03, HDLsCS250VLSI Systems DesignLecture 3: Hardware Design LanguagesFall 2011Krste Asanovic’, John WawrzynekwithJohn LazzaroandBrian Zimmer (TA)CS250, UC Berkeley Fall ‘11Lecture 03, HDLsOutline‣Background and History of Hardware Description‣Brief Introduction to Chisel Part 1‣Next Monday, Chisel Part 22CS250, UC Berkeley Fall ‘11Lecture 03, HDLsDesign Entry‣Schematic entry/editing used to be the standard method in industry and universities.‣Used in commonly until ~2002Schematics are intuitive. They match our use of gate-level or block diagrams.Somewhat physical. They imply a physical implementation.Require a special tool (editor).Unless hierarchy is carefully designed, schematics can be confusing and difficult to follow on large designs.• Hardware Description Languages (HDLs) are the new standard– except for PC board design, where schematics are still used.3CS250, UC Berkeley Fall ‘11Lecture 03, HDLsHardware Description Languages‣Originally invented for simulation.‣Now “logic synthesis” tools exist to automatically convert from HDL source to circuits.‣High-level constructs greatly improves designer productivity.‣However, this may lead you to falsely believe that hardware design can be reduced to writing programs!*‣Basic Idea: language constructs describe circuits with two basic forms:–Structural descriptions: connections of components. Nearly one-to-one correspondence to with schematic diagram.–Behavioral descriptions: use high-level constructs (similar to conventional programming) to describe the circuit function.“Structural” example:Decoder(output x0,x1,x2,x3; inputs a,b)}wire abar, bbar; inv(bbar, b); inv(abar, a); and(x0, abar, bbar); and(x1, abar, b ); and(x2, a, bbar); and(x3, a, b );} “Behavioral” example:Decoder(output x0,x1,x2,x3; inputs a,b){ case [a b] 00: [x0 x1 x2 x3] = 0x1; 01: [x0 x1 x2 x3] = 0x2; 10: [x0 x1 x2 x3] = 0x4; 11: [x0 x1 x2 x3] = 0x8; endcase;} 4Warning: this is a fake HDL!*Describing hardware with a language is similar, however, to writing a parallel program.CS250, UC Berkeley Fall ‘11Lecture 03, HDLsStandard Design MethodologyHDLSpecificationHierarchically defines structure and/or function of circuit.SimulationVerification: Does the designbehave as required with regards to function (and timing, and power consumption)?SynthesisMaps specification to resources of implementation platform (FPGA or ASIC).5Note: This in not the entire story. Other tools are useful for analyzing HDL specifications. More on this later.CS250, UC Berkeley Fall ‘11Lecture 03, HDLsHDL History‣Verilog originated at Automated Integrated Design Systems (renamed Gateway) in 1985. Acquired by Cadence in 1989.‣Invented as simulation language. Synthesis was an afterthought. Many of the basic techniques for synthesis were developed at Berkeley in the 80’s and applied commercially in the 90’s.‣Around the same time as the origin of Verilog, the US Department of Defense developed VHDL (A double acronym! VSIC (Very High-Speed Integrated Circuit) HDL). Because it was in the public domain it began to grow in popularity.‣Afraid of losing market share, Cadence opened Verilog to the public in 1990. ‣An IEEE working group was established in 1993, and ratified IEEE Standard 1394 (Verilog) in 1995. ‣Verilog is the language of choice of Silicon Valley companies, initially because of high-quality tool support and its similarity to C-language syntax.‣VHDL is still popular within the government, in Europe and Japan, and some Universities.‣Most major CAD frameworks now support both.‣Latest Verilog version is “System Verilog” .‣Other alternatives these days:‣Bluespec (MIT spin-out) models digital systems using “guarded atomic actions”‣C-to-gates Compilers (ex: Synfora PICO, AutoESL)6CS250, UC Berkeley Fall ‘11Lecture 03, HDLsVerilog “Issues”‣Designed as a simulation language. “Discrete Event Semantics”‣Many constructs don’t synthesize: ex: deassign, timing constructs‣Others lead to mysterious results: for-loops‣Difficult to understand synthesis implications of procedural assignment (always blocks), and blocking versus non-blocking assignments‣Your favorite complaint here!‣In common use, most users ignore much of the language and stick to a very strict “style”, Large companies post use rules and run lint style checkers. Nonetheless leads to confusion (particularly for beginners), and bugs.7// Gray-code to binary-code convertermodule gray2bin1 (bin, gray); parameter SIZE = 8; output [SIZE-1:0] bin; input [SIZE-1:0] gray; genvar i; generate for (i=0; i<SIZE; i=i+1) begin:bit assign bin[i] = ^gray[SIZE-1:i]; end endgenerate endmodule ‣The real power of a textual representation of circuits is the ability to write circuit “compilers”. Verilog has very weak “meta-programming” support”. Simple parameter expressions, generate loops and case.‣Various hacks around this over the years, ex: embedded TCL scripting.CS250, UC Berkeley Fall ‘11Lecture 03, HDLsChisel‣Experimental attempt at a fresh start to address these issues. ‣Clean simple set of design construction primitives, just what is needed for RTL design (later support for UTL design)‣Powerful “metaprogramming” model for building circuit generators‣Why embedded?‣Avoid the hassle of writing and maintaining a new programming language (most of the work would go into the non-hardware specific parts of the language anyway).‣Why Scala?‣Brings together the best of many others: Java JVM, functional programming, OO programming, strong typing, type inference.‣Still very new. Bugs will show up. Your feedback is needed.‣In class, brief presentation of basics. Ask questions.‣First tutorial document available online. Formal reference later.8Constructing Hardware In a Scala Embedded LanguageCS250, UC Berkeley Fall ‘11Lecture 03, HDLsChisel Acknowlegements9Jonathan BachrachPrincipal developerHuy VoUndergrad research assistant, Chisel DeveloperBrian RichardsFirst actual user (translated FPU Verilog code to Chisel)Yunsup Lee, Andrew WatermanEarly users for processor design mapped to FPGAsScott BeamerEarly user continues to write chisel routers and give feedbackChris CelioPushed the design, given feedback, and written the most Chisel code in writing RiscV codeChris BattenFast C++ template library that inspired Chisel fast