Bits and Pieces of CS250’s ToolflowCS250 Tutorial 2 (Version 091210a)September 12, 2010Yunsup LeeIn this tutorial you will learn what each VLSI tools used in class are meant to do, how they flow,file extensions of their inputs and outputs.Figure 1 shows the CS250 toolflow you will be using for the class. You will use Synopsys VCS (vcs)to simulate and debug your RTL design. After you get your design right, you will use SynopsysDesign Compiler (dc shell-xg-t) to synthesize the design. Synthesis is the process of transformingan RTL model into a gate-level netlist. You will use Synopsys Formality (fm shell) to formallyverify that the RTL model and the gate-level model match. VCS is used again to simulate thesynthesized gate-level netlist. After obtaining a working gate-level netlist, you will use SynopsysIC Compiler (icc shell) to place and route the design. Placement is the process by which eachstandard cell is positioned on the chip, while routing involves wiring the cells together using variousmetal layers. The tools will provide feedback on the performance and area of your design after bothsynthesis and place and route. The results from place and route are more realistic but require muchmore time to generate. After place and route, you will generate and simulate the final gate-levelnetlist using VCS. Finally you will use this gate-level simulation as a final test for correctness andto generate transition counts for every net in the design. Synopsys PrimeTime PX (pt shell)takes these transition counts as input and correlate them with the capacitance values in the finallayout to produce estimated power measurements.Each section or subsection has a list of documents which are provided from Synopsys. The docu-ments are located in the cs250 course locker (~cs250/manuals) which can be accessed through theinstructional machines.ToolsSynopsys VCSVCS is used to simulate your design. The design could be expressed in several different languages,however, we encourage you to use Verilog for this class. For more information on Verilog, take alook at the Language section in this tutorial. VCS takes a set of Verilog files as input and producesa simulator. When you execute the simulator you need some way to observe your design so that youcan measure its performance and verify that it is working correctly. You can instruct the simulatorto automatically write transition information about each signal in your design to a file. There is astandard text format for this type of signal transition trace information called the Value ChangeDump format (VCD). Unfortunately, these textual trace files can become very large quickly, soSynopsys uses a proprietary compressed binary trace format called VCD Plus (VPD). You canview VPD files using a waveform viewer called Synopsys Discover Visual Environment (DVE).• vcs-user-guide.pdf - VCS User Guide• vcs-quick-reference.pdf - VCS Quick ReferenceCS250 Tutorial 2 (Version 091210a), Fall 2010 2Execute SIMVerilogSource(Behav)BehavSimVCSVPDTestOutputsDVE GUIVerilogSource(RTL)VCS Design CompilerFormalityDesign Vision GUIIC Compiler (DP)IC Compiler (P&R)ConstraintsFileVerificationResultsConstraintsStd.CellLibraryRTLSimGateLevelNetlistTimingAreaDelayFileTLU+FilesFloorPlanConstraintsFileGateLevelNetlistTimingAreaLayoutParasiticsFileDelayFileExecute SIMGuidanceFileVPDTestOutputsDVE GUIVCSPostSynSimExecute SIMVPDTestOutputsDVE GUIVCSPostP&RSimExecute SIMVPDTestOutputsDVE GUIIC Compiler GUIPrimeTimeVCDVPD2VCDPowerEstimatesFigure 1: CS250 ToolflowCS250 Tutorial 2 (Version 091210a), Fall 2010 3• vcs dve-user-guide.pdf - Discovery Visual Environment User Guide• vcs ucli-user-guide.pdf - Unified Command Line Interface User GuideSynopsys Design CompilerDesign Compiler takes an RTL hardware description, timing constraints, and a standard cell libraryas input and produces a gate-level netlist as output. To take a closer look at the standard cell libraryyou are using for the class, consult the Process section of this tutorial. Internally, a synthesis toolperforms many steps including high-level RTL optimizations, RTL to unoptimized Boolean logic,technology independent optimizations, and finally technology mapping to the available standardcells. A synthesis tool is only as good as the standard cells which it has at its disposal. You getreports about the critical path of your synthesized design, area and power estimates, and resourcemapping. You can also take advantage of Design Vision to visualize critical paths of your synthesisresults, and schematics of the gate-level netlist.• dc-user-guide.pdf - Design Compiler User Guide• dc-quick-reference.pdf - Design Compiler Quick Reference• dc-user-guide-cli.pdf - Design Compiler Command-Line Interface Guide• dc-user-guide-lp.pdf - Synopsys Low-Power Flow User Guide• dc-user-guide-verilog.pdf - HDL Compiler for Verilog User Guide• dc-user-guide-sysverilog.pdf - HDL Compiler for SystemVerilog User Guide• dc-user-guide-tcl.pdf - Using Tcl With Synopsys Tools• dc-user-guide-tco.pdf - Synopsys Timing Constraints and Optimization User Guide• dc-reference-manual-opt.pdf - Design Compiler Optimization Reference Manual• dc-reference-manual-rt.pdf - Design Compiler Register Retiming Reference Manual• dc-application-note-sdc.pdf - Synopsys Design Constraints Format Application Note• dc dv-user-guide.pdf - Design Vision User Guide• dc dv-tutorial.pdf - Design Compiler Tutorial Using Design VisionSynopsys FormalityFormality is used to formally verify whether or not your RTL implementation and the synthesizedgate-level netlist match. Formal verification utilizes mathematical techniques to compare the logicto be verified against either a logical specification or a reference design. Unlike verification throughsimulation, formal verification does not require input vectors. As it considers only logical functionsduring comparisons, it is independent of the design’s physical properties, such as its layout andtiming.• fm-user-guide.pdf - Formality User Guide• fm-quick-reference.pdf - Formality Quick ReferenceCS250 Tutorial 2 (Version 091210a), Fall 2010 4Synopsys IC CompilerIC Compiler takes as input a gate-level netlist, timing constraints, physical and timing libraries,and it generates as output a layout. It first determines how each gate should be placed on thechip. Then it uses several heuristic algorithms to group related gates together and thus hopefullyminimize routing congestion and wire delay. This tool will