Write and Synthesize a Two-StageRISC-V-v2 ProcessorCS250 Laboratory 2 (Version 082511)Written by Yunsup Lee (2010)Updated by Brian Zimmer (2011)OverviewFor the second lab assignment, you will write an RTL model of a two-stage pipelined RISC-V-v2 (asubset of the RISC-V instruction set) processor using Chisel and synthesize your RTL model. Afterproducing a working RTL model, you will attempt to optimize your design to increase performanceand/or decrease area. The instruction set allows for both a 32 bit or 64 bit datapath, but as a 64bit version will take more time to run through the tools, we will be building a 32 bit version.DeliverablesThis lab is due Monday, September 26th at 1pm. Deliverables for this lab are:• (a) your optimized and verified Chisel source and all of the scripts necessary to completelysynthesize your RTL implementation checked into Git• (b) one assembly test program and one C benchmark program to test your implementation• (c) written answers to the questions given at the end of this document checked into git aswriteup/report.pdf or writeup/report.txtYou are encouraged to discuss your design with others in the class, but you must turn in your ownwork. The two-stage pipeline should perform instruction fetch in the first stage, while the secondpipeline stage should do everything else including data memory access.If you need to refresh your memory about pipelining and the MIPS instruction set, we recom-mend Computer Organization and Design: The Hardware/Software Interface, Fourth Edition, byPatterson and Hennessey.A mandatory prerequisite is to read about the RISC-V architecture, which can be found in theRISC-V Instruction Set Manual on the website. In this lab, you will be implementing a subsetof this instruction set, but to understand what each instruction does, you will need to read therelevant sections of this manual.For more information about using Synopsys VCS for Verilog simulation consult Tutorial 4: Simulat-ing Verilog RTL using Synopsys VCS. To learn more about Synopsys Design Compiler for synthesisplease refer to Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler. Detailed in-formation about building, running, and writing RISC-V assembly and C codes could be found inTutorial 3: Build, Run, and Write RISC-V Programs.Make sure to separate out datapath and memory components from control circuitry. The systemdiagram in Figure 3 can be used as an initial template for your two-stage RISC-V-v2 processorCS250 Lab Assignment 2 (Version 082511), Fall 2011 2implementation, but please treat it as a suggestion. Your objective in this lab is to implement theRISC-V-v2 ISA, not to implement the system diagram so feel free to add new control signals, mergemodules, or make any other modifications to the system. You will need to turn in a diagram of yourdatapath anyway, so it is highly recommended that you draw your datapath from the beginning ina program such as Omnigraffle or Visio, and keep it updated as you design. This reference will bevery useful to speed up debugging.Processor Interface riscvTestHarnessCputestrig_fromhostimem.req_addrimem.req_valtestrig_tohostclkresetInstructionMemoryDataMemoryimem.resp_datadmem.req_rwdmem.req_addrdmem.req_wdatadmem.req_valdmem.resp_dataclkclkFigure 1: Block diagram for RISC-V-v2 Processor Test HarnessWe have given you a 1-stage processor which already has a working interface to a test harnessand memories. The test harness will drive the inputs and check the outputs of your design fora number of tests written in assembly language. These tests are targeted to verify correct func-tionality of every instruction. The test harness includes the data and instruction memories. Wehave provided separate instruction and data memory ports to simplify the construction of thepipeline, but both ports access the same memory space. The memory ports can only access 32-bitwords, and so the lowest two bits of the addresses are ignored (i.e., only imemreq bits addr[31:2]and dmemreq bits addr[31:2] are significant). To make an instruction memory request, setimemreq bits addr to the fetch address and set imemreq val to one. The data will be returnedcombinationally (i.e. there are no clock edges between when a request is made and when the re-sponse returns). To make a data memory request set dmemreq bits rw to zero for a load or one fora store, set dmemreq bits addr to the address, set dmemreq bits data to the store data if needed,and finally set dmemreq val to one. The data will be returned combinationally for loads, while forstores the data will be written at the end of the current clock cycle. Notice that the data write busis a separate unidirectional bus from the data read bus. Bidirectional tri-state buses are usuallyavoided on chip in ASIC designs.CS250 Lab Assignment 2 (Version 082511), Fall 2011 3Test HarnessThere are two test harnesses: one for the Chisel-generated emulator, and another for the Chisel-generated Verilog. You should design your processor such that it passes the emulator testbenchfirst. Then, when you are ready to synthesize your design, you should run the Verilog testbench toensure that there are no bugs in the Chisel verilog generator.We are providing a test harness to connect to your processor model. The test harness is identicalto the one described in Tutorial 4: Simulating Verilog RTL using Synopsys VCS and Tutorial 5:RTL-to-Gates Synthesis using Synopsys Design Compiler. The test harness loads a RISC-V binaryinto the memory. The provided makefile can load both assembly tests as well as C benchmarksto run on your processor. The test harness will clock the simulation until it sees a non-zero valuecoming back on the testrig tohost register, signifying that your processor has completed a testprogram. The testrig tohost port should be set to zero on reset. A very simple test program isshown in Figure 2.# 0x00000000: Reset vector.addi $x1, $x0, 1 # Load constant 1 into register x1mtpcr $x1, $cr16 # Write x1 to tohost registerloop: beq $x0, $x0, loop # Loop foreverFigure 2: Simple test programImplemented InstructionsRISC-V ISA is a research ISA we use in Berkeley. This ISA defines 32-bit, 64-bit operations, includ-ing single and double precision floating point operations, as well as supervisor operations. Consultthe RISC-V Processor Specification for more details about the RISC-V architecture. You may alsowant to read Tutorial 3: Build, Run, and Write RISC-V Programs. For this lab assignment, youwill only be