UC Regents Fall 2009 © UCBCS 250 L11: DRAM2009-10-1John Wawrzynek and Krste Asanovic! with John LazzaroCS 250 VLSI System DesignLecture 11 – DRAMwww-inst.eecs.berkeley.edu/~cs250/TA: Yunsup Lee 1UC Regents Fall 2009 © UCBCS 250 L11: DRAMToday’s Lecture: DRAMTop-down: SDRAM commandsBottom-up: DRAM core cellsDRAM controller design ideas2UC Regents Fall 2009 © UCBCS 250 L11: DRAMDynamic Memory Cells3UC Regents Fall 2009 © UCBCS 250 L11: DRAMRecall: Capacitors in actionI = 0Because the dielectric is an insulator, and does not conduct.After circuit “settles” ...Q = C V = C * 1.5 Volts (D cell)Q: Charge stored on capacitorC: The capacitance of the device: function of device shape and type of dielectric. +++ +++--- ---After battery is removed:+++ +++--- ---Still, Q = C * 1.5 VoltsCapacitor “remembers” charge1.5V 4UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM cell: 1 transistor, 1 capacitorVddCapacitor “Word Line”“Bit Line”p-oxiden+ n+oxide------“Bit Line”Word Line and Vdd run on “z-axis”VddDiode leakagecurrent.Why Vcap values start out at ground.VcapWord LineVdd“Bit Line”5UC Regents Fall 2009 © UCBCS 250 L11: DRAMA 4 x 4 DRAM array (16 bits) ....6UC Regents Fall 2009 © UCBCS 250 L11: DRAMInvented after SRAM, by Robert Dennardwww.FreePatentsOnline.comwww.FreePatentsOnline.comwww.FreePatentsOnline.com7UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Circuit Challenge #1: WritingVddVdd - Vth. Bad, we store less charge. Why do we not get Vdd?VddVddIds = [(µεW)/(2LD)] [Vgs -Vth]^2 , but “turns off” when Vgs <= Vth!VgsVcVgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops!8UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Challenge #2: Destructive ReadsVddVc -> 0++++++++++++++ (stored charge from cell)0 -> VddWord LineRaising the word line removes the charge from every cell it connects to!Must write back after each read.VgsBit Line(initializedto a low voltage)9UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Circuit Challenge #3a: SensingAssume Ccell = 1 fFBit line may have 2000 nFet drains,assume bit line C of 100 fF, or 100*Ccell.Ccell holds Q = Ccell*(Vdd-Vth)dV = [Ccell*(Vdd-Vth)] / [100*Ccell]dV = (Vdd-Vth) / 100 ⋲ tens of millivolts! In practice, scale array to get a 60mV signal.When we dump this charge onto the bit line, what voltage do we see?Ccell100*Ccell10UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Circuit Challenge #3b: SensingCompare the bit line against the voltage on a “dummy” bit line.How do we reliably sense a 60mV signal?[...]“Dummy” bit line.Cells hold no charge.?-+Bit line to senseDummy bit line“sense amp”11UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Challenge #4: Leakage ...VddBit Line+++++++Word Linep-oxiden+ n+oxide------Parasitic currents leak away charge.Diode leakage ...Solution: “Refresh”, by reading cells at regular intervals (tens of milliseconds)12UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Challenge #5: Cosmic Rays ...VddBit Line+++++++Word Linep-oxiden+ n+oxide------Cosmic ray hit.Solution: Store extra bits to detect and correct random bit flips (ECC).Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge!13UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Challenge 6: YieldSolution: add extra bit lines (i.e. 80 when you only need 64). During testing, find the bad bit lines, and use high current to burn away “fuses” put on chip to remove them.If one bit is bad, do we throw chip away?[...]Extra bit lines.Used for “sparing”.14UC Regents Fall 2009 © UCBCS 250 L11: DRAMRecall: Process Scaling6665nm300mmDual CoreScaling: Scaling: The Fundamental Cost DriverThe Fundamental Cost Driver90nm300mm130nm200mm180nm200mm250nm200mm350nm200mmOROR==Twice theTwice thecircuitry in thecircuitry in thesame spacesame space(architectural(architecturalinnovation)innovation)The sameThe samecircuitry in halfcircuitry in halfthe spacethe space(cost reduction)(cost reduction)Half the die sizeHalf the die sizefor the samefor the samecapability thancapability thanin the priorin the priorprocessprocessRecall process scaling (“Moore’s Law”)From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005.1616Process Advances Still Scale PowerProcess Advances Still Scale Powerbut the rate has slowed and collaboration is requiredbut the rate has slowed and collaboration is required..35!m35!m..25!m25!m..18!m18!m..13!m13!m90nm90nm65nm65nm45nm45nm32nm32nmCVCV22 Scaling ScalingDue to reducing V and C (length and width of Cs decrease, but plate distance gets smaller).Recent slope more shallow because V is being scaled less aggressively.15UC Regents Fall 2009 © UCBCS 250 L11: DRAMDRAM Challenge 7: ScalingEach generation of IC technology, we shrink width and length of cell.dV ⋲ 60 mV= [Ccell*(Vdd-Vth)] / [100*Ccell]Solution: Constant Innovation of Cell Capacitors!Problem 1: Number of arrays per chip grows!As Ccell and drain capacitances scale together, number of bits per bit line stays constant.Problem 2: Vdd may need to scale down too!16UC Regents Fall 2009 © UCBCS 250 L11: DRAMPoly-diffusion Ccell is ancient historyVddCapacitor “Word Line”“Bit Line”p-oxiden+ n+oxide------“Bit Line”Word Line and Vdd run on “z-axis”Word LineVdd“Bit Line”17UC Regents Fall 2009 © UCBCS 250 L11: DRAMEarly replacement: “Trench” capacitors18UC Regents Fall 2009 © UCBCS 250 L11: DRAMFinal generation of trench capacitorsThe companies that kept scaling trench capacitors are in the process of going out of business ...19UC Regents Fall 2009 © UCBCS 250 L11: DRAMModern cells: “stacked” capacitors20UC Regents Fall 2009 © UCBCS 250 L11: DRAMMicron 50nm 1-Gbit DDR2 die photo21UC Regents Fall 2009 © UCBCS 250 L11: DRAMMemory Arrays1128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.128Mb: x4, x8, x16SDRAMPRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.32 Meg x 4 16 Meg x 8 8 Meg x 16Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banksRefresh Count 4K 4K 4KRow Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)SYNCHRONOUSDRAMMT48LC32M4A2 – 8 Meg x 4 x