Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011CS250 VLSI Systems DesignLecture 8: Introduction to Hardware Design PatternsJohn Wawrzynek, Krste Asanovic,withJohn LazzaroandBrian Zimmer (TA)UC BerkeleyFall 2011Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011A Difficult Design Problem?2(For today’s lecture, we’ll assume clock distribution is not an issue)A humble shift registerLecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011First Complication: Output Stall3Shift register should only move data to right if output ready to accept next itemWhat complication does this introduce?Need to fan out to enable signal on each flopReady?Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Stall Fan-Out Example4200 bits per shift register stage, 16 stages3200 flip-flopsHow many fanout-of-four gate delays to buffer up ready signal?‣Log4(3200) = 5.82 , ~ 6 FO4 delays!Ready?EnableThis doesn’t include any penalty for driving enable signal wires!Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Loops Prevent Arbitrary Resizing5We could increase size of gates in ready logic block to reduce fan out required to drive ready signal to flop enables…But this increases load on flops, so they have to get bigger--- a vicious cycle!Ready?Ready LogicShift Register ModuleReceiving ModuleLecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Second Complication: Input Bubbles6Sender doesn’t have valid data every clock cycle, so empty “bubbles” inserted into pipelineStage 1Stage 2Stage 3Stage 4Time!Ready!ValidValid?Ready?Stage 1 Stage 2 Stage 3 Stage 4Pipeline DiagramWant to “squeeze” bubble out of pipeline!Valid!ReadyLecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Logic to Squeeze Bubbles7Can move one stage to right if Ready asserted, or if there are any bubbles in stages to right of current stageReady?Enable?Valid?Fan-in of number of valid signals grows with number of stagesFan-out of each stage’s valid signal grows with number of stagesLonger combinational paths as number of pipeline stages grows(Assume same enable logic on every stage) Valid?Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011A Common Design Problem8The shift register is an abstraction of any synchronous pipelined block of logic that accepts input data and produces output data, where input and output might not be ready every clock cycleHow to manage growth in control logic complexity?Valid?Ready?Stage 1 Stage 2 Stage 3 Stage 4Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Solution: Decouple Units with FIFOs9ConsumerProcessing PipelinePipeline only cares whether space in FIFO, not about whether consumer can take next valueBreaks combinational path between pipeline control logic and consumer control logicFor full throughput with decoupling, need at least two elements in FIFOWith only one element, have to ping-pong between pipeline enqueue and consumer dequeueAllowing both enqueue and dequeue in same cycle to single-element FIFO destroys decoupling (back to a synchronous connection)Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Decoupled Design DisciplineMany large digital designs are divided into local synchronous pipelines, or units, connected via decoupling FIFOsApprox. 10K-100K gates per unitDecoupled units may have different clocksIn which case, need asynchronous FIFOs10Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Hardware Design PatternsDecoupled units are an example of a design patternPattern: Solution to a commonly recurring design problemIdea of patterns and a “pattern language” first proposed for building architecture (Christopher Alexander)“Pattern language” is an interlocking set of design patternsProbably better named a “pattern hierarchy”Alexander proposed single pattern language covering architecture from design of cities to design of roof capsPatterns popular in software engineering (“Gang of Four”) and now being used in Par Lab (“Our Pattern Language (OPL)”) to architect parallel softwareThis semester continues an experiment to see if we can teach hardware design using patterns11Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Digital Design Through PatternsApplication(s)MP3 bit stringAudioHardware (RTL)MP3 bit stringAudioBerkeley Hardware Pattern Language12Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011BHPL GoalsBHPL captures problem-solution pairs for creating hardware designs (machines) to execute applicationsBHPL Non-GoalsDoesn’t describe applications themselves, only machines that execute applications and strategies for mapping applications onto machines13Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011BHPL describes Machines not ApplicationsDense Linear AlgebraSparse Linear AlgebraSpectral MethodsFSMsGraph AlgorithmsCircuitsN-Body MethodsDynamic ProgrammingComputational PatternsGraph TraversalStructured GridsUnstructured GridsGraphical ModelsPipelinesModel-View-ControllerEvent BasedProcess ControlAgent&RepositoryStructural PatternsMap-ReduceIterationLayered SystemsTask GraphsApplications (including OPL patterns)MachinesBHPLMapping Patterns14Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Vocabulary for Machines15Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Why a Vocabulary?Need a standard graphical and textual language to describe the problems and solutions in our pattern languageReally just a consistent way of drawing and talking about block diagrams16Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Machine VocabularyMachines described using a hierarchical structural decompositionUnits (generalized processing engines)MemoriesNetworks (connect multiple entities)Channels (point-to-point connections)(Memories, Networks, Channels are specialized Units)17Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Unit typesMemories, Networks, and Channels are also units, just with specialized symbol to convey their main intended purpose.Memories store data.Networks connect multiple entitiesChannels are point-point communication pathsHigh-level channels show primary direction of information flowMight have wires in other direction to handle flow-control etc.18Lecture 8, Hardware Design Patterns CS250, UC Berkeley, Fall 2011Hierarchy within UnitInput PortOutput PortInput/Output PortPorts