CS250 VLSI Systems Design Fall 2020 John Wawrzynek with Arya Reais Parsi virtual GSI Lecture 01 Introduction 1 CS250 UC Berkeley Spring 2017 First Thing This class has always been and will continue to be highly interactive not recorded It is like a studio based art class Students show and discuss their art and get feedback and ideas from other students and the instructor Minimal emphasis on lectures We found this to be a very effective for students to advance their design skills But it s success depends on commitment by everyone Everyone is expected to stay engaged and offer comments and questions Challenging now in the days of the pandemic It can work over zoom but it takes more effort by all of to stay engaged In my experience with teleconferencing and many zoom meetings over these months teleconferencing works best with video enabled If your situation prohibits you from comfortably keeping your video on Stay muted but un mute and interrupt at any time please let me know Otherwise I ll expect that you keep it on Lecture 01 Introduction 1 2 CS250 UC Berkeley FA20 courses Design Methodologies John Wawrzynek pronounced Warsnik Professor in EECS Berkeley faculty since 1989 Teaching CS61c EECS151 251A other hardware and architecture Research Computer Architecture Recon gurable Computing Digital Advanced Wireless Systems Administrative CS Vice chair for Graduate Chair Berkeley Campus Con ict of Interest Committee Degrees MSEE UIUC PhD Caltech Start ups Former life professional musician bass Buffalo NY Matters Lecture 01 Introduction 1 3 CS250 UC Berkeley FA20 3 The context for CS250 Number 1 reason for students to enroll in CS250 Gain more experience in digital design specifically targeting custom ICs Components of Digital Design 1 Logic and Transistor Circuits and low level blocks how to achieve desired function of low level chip building blocks state transitions and clocking performance cost power tradeoffs physical realization concerns oorplanning clock distribution pwr distribution Provides Bottom up knowledge Lecture 01 Introduction 1 4 CS250 UC Berkeley FA20 The context for CS250 Components of Digital Design 2 Chip Architectures and high level blocks How building blocks are assembled to achieve high level functionality Processor Cores CPUs chip multiprocessors CMP Field Programmable Gate Arrays FPGAs Coarse grain Recon gurable Arrays CGRAs Domain processors GPU DNN engines DSPs algorithm speci c accelerators graph processor video codec encryption engine The programmable architectures start from a standard execution model ISA Accelerators start from an algorithm or set of algorithms We learn their structure and degrees of freedom in functionality and implementation tradeoffs Provides Top down knowledge Lecture 01 Introduction 1 5 CS250 UC Berkeley FA20 The context for CS250 Components of Digital Design 3 Design Representations Methodologies Tools Representations give us a way to abstract enter manipulate analyze our design leading to an implementation Ex data ow graphs Bool Equations Verilog logic gate netlists GDS Methodology roadmap that we follow to implement our designs The tools analyze and automate aspects of implementaion and optimization convert from one from to another Lecture 01 Introduction 1 6 CS250 UC Berkeley FA20 You ve learned the basics already What we assume you know at this point 1 Circuits Basic logic design and optimization CMOS implementations of logic functions and state elements Structure of basic building blocks arithmetic FSMs memory blocks edge triggered synchronous clocking 2 Architecture Basic RISC CPU structure FPGA fabric structure and in principle how to design an accelerator 3 Tools some design ow for ASIC or FPGA from Verilog VHDL to mapping to chip or fabric Most likely with industry standard tools from Cadence Synopsys and Mentor Graphics We assume that you understand how to map function to circuits but not much experience with optimization Lecture 01 Introduction 1 7 CS250 UC Berkeley FA20 Berkeley Digital Design Classes CS152 252 CPU structure CMPs memory systems on chip interconnect NoCs EECS151 251A Focus on RISC V microarchitecture Xilinx FPGA fabric architecture Synchronous logic design Arithmetic blocks ASIC FPGA design ows EE241B Extensive CMOS transistor level circuit analysis and optimization for EE250 More practice with design tools Synopsys with academic process Alternative design methodology Chisel based not Verilog VHDL Emphasis on design optimization Design Space Exploration DSE performance cost power design kit PDK Lecture 01 Introduction 1 8 CS250 UC Berkeley FA20 Design Optimization Industrial View Meeting some set of prescribed or desired constraints on power cost and performance How do we de ne these Academic View Mapping the Pareto Optimal Frontier Pareto Optimal Frontier Performance tasks sec high performance at high cost low performance at low cost How do we nd these points Cost of components Lecture 01 Introduction 1 9 CS250 UC Berkeley FA20 Design Space Exploration CS250 has traditionally focussed on methodology for DSE practice on some particular function accelerator processor Processor cores Memory controllers image processors cordic blocks audio processor radio communications blocks Mapping the Pareto frontier has been the goal What are the tradeoffs to be made Pipelining Serialization versus parallelization gives us a way to trade area for performance and area for power Designs are speci ed as parameterized generators allowing parameter sweeps to build and analyze a variety of designs Chisel helps in building generators Lecture 01 Introduction 1 10 CS250 UC Berkeley FA20 Chisel Constructing Hardware In a Scala Embedded Language Embeds hardware description language in Scala using Scala s extension facilities Hardware module is just data structure in Scala Different output routines generate different types of output C FPGA Verilog ASIC Verilog from same hardware representation Full power of Scala for writing hardware generators Object Oriented Factory objects traits overloading etc Functional Higher order functions anonymous Compiles to JVM Good performance Java functions currying C code Chisel Program Scala JVM FPGA Verilog ASIC Verilog interoperability C Compiler Software Simulator FPGA Tools FPGA Emulation ASIC Tools GDS Layout 11 EE141 ASIC tools PDKs Fabrication Chip design relies heavily on CAD tools Logic synthesis mapping layout functional timing power analysis veri cation And on process design kits PDK
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