Design of a 4-Bit ALUAgendaAbstractIntroductionLogic UnitSlide 6Slide 72X1 MultiplexerD Flip-FlopFull AdderFull Adder Wave_FormY-Gen SchematicY-Gen and AU Logic VerificationAU (Arithmetic Unit)Longest Path CalculationsSlide 164 Bit_ALU Schematic4 Bit_ALU Test_Bench4 Bit ALU Wave_FormLayout and LVSConclusionsAcknowledgements01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan1Design of a 4-Bit ALUPresented byPreeti Chauhan, Aung Moe, & Harsirat Mangat Advisor: Professor David Parent12/06/2004EE166 Project Presentation01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan2Agenda•Abstract•Introduction: Basic ALU Blocks -- Logic Unit -- Arithmetic Unit -- 2x1 Multiplexer -- D Flip-Flop•4-Bit ALU -- Schematic -- Size Calculations -- Layout -- Verification -- Simulation•Conclusions01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan3Abstract•We designed a 4 Bit ALU that operated at 200 MHz and use 650mW of Power and occupied an area of 649 x 240 m201/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan4IntroductionBasic ALU Blocks 4-Bit ALUReference: Digital Logic Circuit Analysis & Design by Nelson, Nagle, Irwin, and Carroll01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan5Logic UnitLogic verification:Schematic:S1 S0 A B F0 0 0 0 0 AND0 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 0 OR0 1 0 1 10 1 1 0 10 1 1 1 11 0 0 0 1 NOT1 0 0 1 11 0 1 0 01 0 1 1 01 1 0 0 0 XOR1 1 0 1 11 1 1 0 11 1 1 1 0Truth TableF = S1’AB+S0AB’+S0A’B+S1S0’A’01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan6Logic UnitLayout:LVS:01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan7Logic UnitSimulation:Delay:01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan82X1 Multiplexer01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan9D Flip-Flop01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan10Full AdderWp =6 um: Wn=4.05umWorst Case Delay = 0.627nsCout = AB+AC+BCY = A xor B xor C = ABC + (A+B+C) Cout01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan11Full Adder Wave_FormDelay =677n –50n = 627ns01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan12Y-Gen SchematicWp = 5.55um Wn =3.45umDelay = 0.86 ns01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan13Y-Gen and AU Logic VerificationFunction S1 S0 Y CinAddition 0 0 B 0Substraction 0 1 Not B 1Increment 1 0 0 1Decrement 1 1 1 0Y = S1’S0’B + S0B’+S0 S1 = S0 + (S1B)Cin = S1 + S001/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan14AU (Arithmetic Unit)Cell Width =30 umCell Length = 125 umDelay = 0.627+0.86+0.4 = 1.887nsXor01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan15Longest Path Calculations12345678No of Logic Levels:XOR = 3AND = 2INV =1NAND =1DFF =4Delay = 5ns/19 = 0.2ns01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan16Longest Path CalculationsnsnsPHL26.0195Note: All widths are in micronsand capacitances in fF01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan174 Bit_ALU Schematic01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan184 Bit_ALU Test_Bench01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan194 Bit ALU Wave_Form01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan20Layout and LVS01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan21Conclusions•We are able to design a 4 Bit ALU which run at 200mHz with 600mW of power •Should work in the same account and consult with group member to get a good layouts•More than 100 hrs of work01/18/19 Aung Moe, Harsirat Mangat, Preeti Chauhan22Acknowledgements•Professor David Parent •Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software donation•Thanks to my wife/husband for putting up with
View Full Document
Unlocking...