Design of 4-bit ALUAgendaAbstractIntroductionFunction TableBlock DiagramProject SummaryLongest Path Calculation (Arith. Unit)Schematic – Top LevelD Flip FlopArithmetic UnitLook Ahead Carry GeneratorSuper BufferLogical UnitLayoutVerificationSimulation-1(Arith.Unit)Simulation –2 (Logical Unit)ResultsCost AnalysisSummaryAcknowledgements1Design of 4-bit ALURevati IngaleMadhuri KakulavarapuAdvisor: David W. Parent17th May 20042Agenda•Abstract•Introduction–Why–Simple Theory–Back Ground information (Lit Review)•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•Goal is to design a 4-bit ALU driving up to 30fF.•Arithmetic operations are A+B, A+B+1, A+ B`, A– B, Transfer A, Transfer B, A + 1, B -1. •Logical operations are A Ex-OR B, A AND B, A OR B, NOT A.•The data should be transferred at clock rates of 200 MHz , with 1ns setup and hold times.•Maximum power is 100mW.•Maximum area is 500×500 µm24IntroductionWhy this project?ALU is a building block of several circuits.•Challenging to design a 16 logic level design working at 5ns.•Challenging to layout.•Design consists of different kinds of logic… Look Ahead Carry Generator logic, Full adder, Subtractor, Transfer Data, DFF, Super Buffer, MUX, Transmission gate, Decoders, Inv, Nand, Nor, Ex-Or, etc.5Function TableA, B = 4 Bit Input, X = don’t care ConditionM , S0, S1 = Status Control PinCin = Carry in; Cout = Carry Out6Block DiagramDecoderSuper BufferCarry GeneratorAdderXOR AND OR INVMUX-2Subtractor & TransferBank of 9 DFFsBank of 5 DFFsArithmetic UnitLogical UnitT-gate Based MUX7Project Summary•The Look Ahead Carry logic makes the Arithmetic unit much faster than the conventional Ripple Carry adder. •The ALU performs Eight Arithmetic functions and Four Logical functions at 200MHz.8Longest Path Calculation (Arith. Unit)Note: All widths are in microns and capacitances in fF.Time Delay at complex gate like XOR is bit more than delay at INV etc.Logic LevelGate Cg to Drive#CDNs #CDPs #LNs #LPs Wn Wp Cg of gate 1 XOR2 30 3 3 2 2 4.05 6.45 17.82 INV 17.8 1 1 1 1 3.15 4.65 13.13 NOR2 13.1 2 3 1 2 2.1 6.3 14.44 NAND2 14.4 3 2 2 1 2.55 2.85 9.15 INV 9.1 1 1 1 1 3.15 4.65 13.16 NOR2 13.1 2 3 1 2 2.1 6.3 14.47 NAND3 40 5 3 3 1 9.6 8.4 308 INV 50 1 1 1 1 6.75 10.35 259 INV 25 1 1 1 1 2.25 3.45 9.710 XOR2 40 3 3 2 2 4.05 4.05 17.811 NAND2 40 3 2 2 1 4.5 4.95 1612 XOR2 20 3 3 2 2 4.05 6.45 17.813 INV 17.8 1 1 1 1 2.25 3.45 9.714 NAND3 9.7 5 3 3 1 2.4 2.1 7.615 INV 40 1 1 1 1 4.5 6.75 1.59Schematic – Top Level10D Flip Flop Decoder11Arithmetic Unit12Look Ahead Carry Generator2 Select Pin Mux13Super BufferT gate for Mux14Logical Unit15Layout16Verification17Simulation-1(Arith.Unit) M, S1, S0, Cin are set for A-B operation and A3, A2, A1, A0 are set to 1111.18Simulation –2 (Logical Unit)M, S1,S0 are set for XOR operation and A3,A2,A1,A0 are set to 0110.19Results•The ALU performs all 12 functions at a 200Mhz clock and a load of 30fF.•Worst-case Power dissipation is 26.7 mW.•Area of the layout is 530×515µm2.20Cost Analysis•Time spent on each phase of the project– Logic design 1 week.– Logic check 1 week.–Gate level design 1 week.–Integration of schematic blocks 2 weeks.–Timing check 2 weeks.–Layout 3 weeks.–Post extraction check 3 days.21Summary•Designed and tested almost all the design units that we learnt in the class. •Designed a 4-Bit ALU that performs eight arithmetic and four logical functions at 200MHz frequency with setup and hold time 1ns, driving up to 30fF. •This circuit can be used as a building block for 16/32-bit ALU.•The Logic design can be modified to perform more functions.22Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Professor David W. Parent for his
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