4-BIT ARITHMETIC LOGIC UNITABSTRACTINTRODUCTIONPowerPoint PresentationSlide 5Logic And Arithmetic Function TableLogic Verification in NC VerilogLong Path Sizing:DFF Sizing:SchematicOverall schematic with DFFLayoutDRC and ExtractionLVS REPORTALU Test Bench for Logic functionLogic outputALU test bench for Arithmetic functionArithmetic function outputPower waveformSummaryLesson LearnedThanks to…14-BIT ARITHMETIC LOGIC UNIT MOTOROLA SN54/74LS181Arora ShaliniGuttal PratibhaModgi ChaitaliShanmugam RamyaAdvisor: Dave ParentDate: 05 -11- 052ABSTRACT•The SN54/74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible functions.Provides 16 Arithmetic Operations Provides all 16 Logic Operations •Operating Clock Frequency = 200MHz•Area = (446 X 219)µm•Power = 12.26 mW3INTRODUCTION Now the current trend in the semiconductor industry is towards high speed and high density .CMOS Technology provides this to support the market needs. In the project, we designed 4 bit ALU using static CMOS technology whichIntroduced us to Cadence Software tools.Taught us design techniques to meet the specification.Improved our Debugging and testing skill.Enhanced our team spirit.4Design FlowDesign FlowSpecificationLogic VerificationTransistor sizingSpice SimulationCell based layoutPower and RoutingPost Extraction5Logic Circuit 4-Bit ALU [ Motorola SN54/74LS181 ]LONG PATH6Logic And Arithmetic Function Table7Logic Verification in NC Verilog8Long Path Sizing:Cell WN (µM)WP (µM)Cg (fF)Tphl (ns)TargetedTphl (ns)SchematicTphl (ns) ExtractedInv 3.35 5.55 95.97 0.15 0.15 0.14AOI33 5.85 8.4 245.73 1 1 0.901AOI5432Decomposed into Nand5, nand4, nand3, nand2, inv.41.53 0.9 0.74 0.68EX-OR2 3.3 4.35 75.46 0.5 0.49 0.46Nand4 3.45 2.4 34.8 0.5 0.49 0.45INV 2.95 4.9 50 0.15 0.15 0.14Long Path through logic= 3.2 ns9DFF Sizing:CellWN (µM)WP (µM) Cg (fF)Tphl (ns)TargetedTphl (ns)SchematicTphl (ns) ExtractedNand (slave) 3.0 2.5550 0.7 0.69 0.66Keeper Mux 1.5 1.5Driver Mux 5.7 9.45Master Nand 3.3 5.4Keeper Mux 1.5 1.5Driver Mux 4.65 9.3Total time= Time through logic+ Time through DFFTotal time: 3.2ns+ 1.4ns=4.6ns10Schematic11Overall schematic with DFF12Layout13DRC and Extraction14LVS REPORT15ALU Test Bench for Logic function16Logic outputInput A3A2A1A0 = 1010B3B2B1B0 = 1001M=1Cn=0S3S2 S1 S0 = 0000 Logic function¯¯_ =AF3F2 F1 F0 = 0101S3S2 S1 S0 = 1111 Logic function =AF3F2 F1 F0 = 101017ALU test bench for Arithmetic function18Arithmetic function outputInput A3A2A1A0 = 1010B3B2B1B0 = 1001M=0Cn=1S3S2 S1 S0 = 0000 Arithmetic function =AF3F2 F1 F0 = 1010S3S2 S1 S0 = 1111 Arithmetic function =A minus 1F3F2 F1 F0 = 100119Power waveformPower = 61.34 mW / 5 clocks = 12.26 mW20Summary•Our design met all the specification, speed 263 MHz, area (446 X 219)µm, Power 12.26 mW, Power density 12.55 W/cm2•We verified all 16 logic and arithmetic functions.21Lesson Learned•Understand the design flow.•Use cell based design.•Do DRC and LVS for each cell.•Have a rough sketch of the overall floor plan before you layout.•Keep track of timing.22Thanks to…•Prof. Dave Parent for all his help.•Cadence Lab and Humming bird software.•Classmates for their input.•Burger King.•AT&T and Cellular
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