4-Bit ALUAgendaAbstractIntroductionSlide 5Project SummaryLongest Path CalculationsD Flip Flop - SchematicD Flip Flop – Layout, LVSDFF Rise and Fall TimeSchematicALU - LayoutVerification (LVS for ALU)Transient Delay and PowerCost AnalysisLessons LearnedSummaryAcknowledgements14-Bit ALU4-Bit ALUChun-Wai LeeShiela ValencianoAdvisor: Dr. David Parent12/05/052AgendaAgenda•Abstract•IntroductionWhy Background information•Project Summary•Project Details•ResultsSchematicsLVS ReportsLayoutsSimulations•Summary3Abstract•The design consists of a 4-bit Arithmetic Logic Unit (ALU) that contains: AND2, OR2, XOR, Full ADDER, DFF•Design Area = 283.8 x 325.6 μm2•Maximum Power = 30 mW4IntroductionIntroduction•An ALU is the high-speed CPU circuit that performs calculations and comparisons•This project illustrates the design and functions of an ALU5IntroductionIntroduction•The design consists of an ALU that manipulates two 4-bit inputs. These inputs produce an output that corresponds to the output selector lineSel1 Sel2 Output0 0 AND0 1 OR1 0 XOR1 1 ADDER•The table displays the possible outputs6Project SummaryProject Summary•The project design utilizes parallel computing so that the clock resources are used efficiently•AND, OR, XOR, and ADDER that are cascade together generate outputs in parallel at the MUX input7Longest Path CalculationsnsnsPHL5.105Note: All widths are in micronsand capacitances in fF T pave Cg Wn ( X 10^-4) Wp ( X 10^-4) New Cg1 DFF 2 INV 0.5ns 30ff 1.5 2.55 6.91ff3 AOI Mux 0.5ns 7ff 1.8 3.09 8.33ff4 INV 0.5ns 8ff 1.5 2.55 7ff5 INV 0.5ns 7ff 1.5 2.55 7ff6 AOI 0.5ns 7ff 1.5 2.55 7ff7 INV 0.5ns 7ff 1.5 2.55 7ff8 AOI 0.5ns 7ff 1.5 2.55 7ff9 INV 0.5ns 7ff 1.5 2.55 7ff10 DFF8D Flip Flop - SchematicD Flip Flop - Schematic9D Flip Flop – Layout, LVSD Flip Flop – Layout, LVS10DFF Rise and Fall TimeDFF Rise and Fall Time•Setup Rise Time = 1.15ns•Setup Fall Time = 0.71 nsHold Rise and Fall Time11SchematicSchematic12ALU - LayoutALU - Layout13Verification (LVS for ALU)Verification (LVS for ALU)14Transient Delay and PowerTransient Delay and Power15Cost AnalysisCost Analysis•Time spent on each stage of the projectDesigning logic: 1 weekVerifying logic: 1 weekVerifying timing: 2 weeksLayout: 3 weeksPost extracted timing: 3 days16Lessons LearnedLessons Learned•How to use Cadence tool •How to design an integrated circuit•How to apply knowledge learned in class into lab work•How to construct an efficient design•How to fix LVS errors•Work on the lab early in the morning!!!17SummarySummary•The project is an application of the knowledge learned in class through circuit testing and design •Designed a 4-Bit ALU at 200MHz frequency with setup and hold time at1ns, driving up to 30fF •This circuit can be used as a building block for 16/32-bit ALU•The Logic design can be modified to perform more functions •Design Area = 284 x 325 μm2•Maximum Power = 30 mW18Acknowledgements•Thanks to Professor David W. Parent for his guidance. •Thanks to Cadence Design Systems for the VLSI lab•Thanks to the help from EE166
View Full Document
Unlocking...