64-Bit AND GateAgendaAbstractIntroductionProject SummaryLongest Path CalculationsSchematic with worst case pathFinal LayoutVerificationNCVerilogTransient Simulation tphlTransient Simulation tplhTime ScheduleLessons LearnedSummaryAcknowledgements164-Bit AND GatePhong NguyenSteve TurnerHarpreet DhillonMahrang SaeedAdvisor: Dave Parent5/8/062Agenda•Abstract•Introduction–What we learned–What it’s used for–Theory•Project Summary•Project Details•Results•Time schedule•Conclusions3Abstract•Designed a 64 bit AND gate that operates at 400 MHz and occupies an area of 807x320um2.4Introduction•By doing this project, we learned how to do a full custom IC design.•64-bit AND gate is useful in doing 64-bit processing.A/32 B/32 Y/10 0 00 1 01 0 01 1 15Project Summary•400 Mhz 64 bit and gate•3.65 % error between worst case and best case input vectors•Tplh equals 2.1ns and Tphl equals 1.57ns•Power = 2.35 mW @ 400 MHz•Power = 1.17 mW @ 200 MHz6Longest Path CalculationsWn Wp Cint Cload Cint+Cg8bitcellnand2 3.00E-04 3.00E-04 5.00E-15 1.51E-14 2.01E-14nor2 3.00E-04 6.00E-04 5.00E-15 7.55E-15 1.26E-14nand2 2.25E-04 2.25E-04 5.00E-15 1.01E-14 1.51E-14last8bitcellnor2 1.95E-04 4.05E-04 5.00E-15 1.08E-14 1.58E-14nand2 3.15E-04 3.30E-04 5.00E-15 2.27E-14 2.77E-14nor2 3.75E-04 9.75E-04 5.00E-15 3.00E-14 3.50E-14dffNAND2 (Slave) 8.10E-04 8.10E-04 5.00E-15 1.01E-14 1.51E-14Driver Mux (Slave) 9.45E-04 5.40E-04 5.00E-15 2.69E-14 3.19E-14NAND2 (Master) 7.50E-04 8.40E-04 5.00E-15 2.49E-14 2.99E-14Driver Mux (Master) 7.80E-04 4.35E+00 5.00E-15 2.66E-14 3.16E-147Schematic with worst case pathblackcell: flip-flop x 64redcell: 8bit cell x 8bluecell: last 8bit cell8Final Layout9Verification10NCVerilogonly time when all bits are 1, output is 111Transient Simulation tphl12Transient Simulation tplh13Time ScheduleVerifying TimingLayoutPost Extracted TimingVerifying LogicTime2 Weeks1 Week2 Weeks1 Week14Lessons Learned•Before starting layout spend time on making a floor plan •Using Cell based design makes it easy & It reduces debug time•Time management is the main key to complete any project•Also pay attention to best case delay as well•See professor more often, keep updated15Summary•It can be used for 64 Bit Processing•Max. Frequency - 400 Mhz •Error between worst and best case input vectors is only 3.65 % •Tplh equals 2.1ns and Tphl equals 1.57ns•Power = 2.35 mW @ 400 MHz•It can be used in a bigger project16Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Professor Parent for his time &
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