4bit-ALU (Arithmetic Logic Unit)AgendaAbstractIntroductionProject Details1bit-ALU Logic4-to-1 Mux4-1 Mux4-1Mux Test Bench1-bit Adder4-bit Full AdderDFF LayoutDFF Test BenchLongest Path Calculations4-ALU Schematic4-ALU LayoutSchematic Test BenchLVSSimulationLessons LearnedSummaryAcknowledgment14bit-ALU (Arithmetic Logic Unit)Lam NguyenVinh NguyenThe DaoAdvisor: Dr. David ParentDate: 12/05/052Agenda1. Abstract2. Introduction - Why? - Background Information3. Project Summary - Schematic - Layout - LVS report -Longest Path Calculations -Lessons Learned4. Summary5. Acknowledgements3AbstractOur designed project 4-ALU performs the following functions:•AND•OR•XOR •ADDERArea = 390µm×590µm =0.23µ m24Introduction•ALU is a basic fundamental unit of any computing system.•Understanding how an ALU is designed and how it works is a benefit to build any advanced logic circuits.•Using this experience, we can have a basic to design a more complex IC.5Project Details•Create Schematics and layouts for And, Or, Xor, Adder, flip-flop, and Mux in the Cadence tool.•Test the schematics by using test bench.•Create Schematic and layout for 1 bit ALU •Run DRC, extract and LVS for 1 bit ALU.•Connect Cout of the first bit to Cin of the second bit and continue to have 4 bit ALU.•Run the DRC, extracted LVS and simulation to check the final design.61bit-ALU LogicDFFLogicDFFThe design uses the concept of parallel operations.74-to-1 Mux ALU handles two inputs of 4 bits each to produce a required output based on the output selectionS0 S1 Output0 0 And1 0 Or0 1 Xor1 1 Adder84-1 MuxWp = 9µWn = 4.5µ94-1Mux Test BenchTime delay:τ = 0.5ns101-bit AdderWp = 7.8µ Wn = 9µ114-bit Full AdderTime delayτ = 1.5ns12DFF Layout13DFF Test BenchTime delayτ = 1.2ns14Longest Path Calculations154-ALU Schematic164-ALU Layout17Schematic Test Bench18LVS19SimulationSelect S0 =1 and S1=1 to have the longest path20Lessons Learned•Using Cadence tool•Designing an integrated circuit to met a specification.•Fixing errors from LVS report and extracted schematic file.•Using a same height for each layout cell to reduce the area.21Summary•Our designed 4-bit ALU can operate for the following operations: And, Or, Xor, Add•Our project has 372 transistors and 20 terminals.•The delay propagation is 5ns.•Area = 390µm×590µm =0.23µ m222Acknowledgment•Thanks to professor David Parent for teaching and helping us throughout this project.•Thanks to Cadence Design Systems for VLSI
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