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SJSU EE 166 - 4 Bit Arithmetic Logic Unit

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4 Bit Arithmetic Logic UnitAgendaAbstractIntroductionBlock diagram of 4 bit ALUProject DetailsDFFLong path calculationsFull Adder SchematicFull Adder LayoutFull Adder LVS Report2-to-1 MUX schematic4-to-1 MUX layout4-bit ALU schematic4-bit ALU layout4 bit ALU(LVS Report)DFF schematicDFF layoutDFF LVS report4 bit ALU with DFF schematic4 bit ALU with DFF layout4 bit ALU with DFF LVS reportTransient AnalysisWorst case (Tphl)Worst case (Tplh)Post extraction simulationResultsCost AnalysisAcknowledgements4 Bit Arithmetic Logic UnitPresented byIpsita Praharaj, Shalaka GhawateAdvisor: Dr. David ParentDate:05/11/04Agenda•Abstract•Introduction - why - Simple Theory - Background•Summary of results•Project Details•Cost Analysis•ConclusionsAbstract•Goal is to design a 4-bit ALU driving upto 30fF that can perform the following operations -FULL ADDER -AND -OR -NORIntroduction•ALU is a building block of several circuits.•Understanding how an ALU is designed and how it works is essential to building any advanced logic circuits.•Using this knowledge and experience, we can move on to designing more complex integrated circuits.•Design consists of different kind of logic…Ripple carry adder, full adder, AND, OR, NOR, DFF, MUX.Block diagram of 4 bit ALUBank of 10 D FF 4:1 MUXBank of 5 D FF Logic UnitNOR2OR2AND2Arithmetic UnitFull AdderProject Details-There are total of 19 pin outs in our design. including VDD and GND. -There are 9 D flip-flops at the input and 4 at the output. -There is a 4:1 MUX to select the output. -Create schematics and layouts for adder, AND, OR, MUX, in the cadence tool. -Test the schematic using test bench. -Create schematic and layout for 1 bit ALU now using the schematics for the basic logical units. -Test the schematic for 1 bit ALU.-Create the single bit ALU to create a 4 bit ALU layout.-Run DRC extracted and LVS check to verify the design.DFF•DFF are placed on either side of the combinational logic.•Hold time= 0.586n(Fall) =0.515n(Rise)•Setup time=0.521n(Fall) =0.450n(Rise)Long path calculationsCELL Cg or Cin of loadNSN NSP N M WN WPINV1 3.00E-14 1 1 1 1 1.52E-04 2.71E-04MUX1 7.0839E-15 2 2 6 6 1.64E-04 2.82E-04INV2 7.4892E-15 1 1 1 1 1.813E-04 3.27E-04MUX2 1.7009E-14 2 2 6 6 1.74E-04 2.96E-04INV_C 7.883E-15 1 1 1 1 1.88E-04 3.40E-04AOI_SUM 1.5777E-14 2 2 4 2 2.28E-04 4.02E-04AOI_C 1.7703E-14 2 2 4 2 2.48E-04 4.36E-04INV_C 1.1466E-14 1 1 1 1 2.53E-04 4.59E-04AOI_C 2.045E-14 2 2 4 2 2.75E-04 4.84E-04INV_C 1.2747E-14 1 1 1 1 2.21E-04 3.99E-04AOI_C 2.081E-14 2 2 4 2 2.79E-04 4.91E-04INV_C 1.2917E-14 1 1 1 1 2.35E-04 4.26E-04AOI_C 2.2184E-14 2 2 4 2 2.81E-04 4.94E-04Full Adder SchematicFull Adder LayoutFull Adder LVS Report2-to-1 MUX schematic4-to-1 MUX layout4-bit ALU schematic4-bit ALU layout4 bit ALU(LVS Report)DFF schematicDFF layoutDFF LVS report4 bit ALU with DFF schematic4 bit ALU with DFF layout4 bit ALU with DFF LVS reportTransient AnalysisWorst case (Tphl)Worst case (Tplh)Post extraction simulationResults•The ALU performs all 4 functions at a 200Mhz clock and a load of 30fF.•We meet the power specifications.•Area of the our layout=192micron*375micron.Cost Analysis•Time spent on each phase of the project. - Logic design 1 week. - Logic check 1 week -Individual schematic 5 days - Integration of schematic blocks 1 week - Layouts 2 weeks - Post extraction check 2 daysAcknowledgements•Thanks to Cadence Design systems for the VLSI labs•Thanks to Professor David Parent for his


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