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SJSU EE 166 - Midterm 2

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EE 166: Midterm 2 NAME: 1Question 1 (15PTS): You are a verification engineer working on a new process line. You have gathered some data from the circuit in Figure 1and is shown in Figure 2. Extract VTN from the data in Figure 2. Figure 1: Schematic of circuit used to gather data. Figure 2: Plot SQRT(ID) vs. VGS =VDS (Saturation Mode). VTN=? (10pts) Does this device demonstrate velocity saturation (5pts)? (Explain your answer.) Note: This is the square root of ID!EE 166: Midterm 2 NAME: 2Question 2(15pts): You have just measured the output of a five-stage ring oscillator. What is the average propagation delay of this circuit? (10PTS) Which circuit below oscillates at the highest frequency? (5PTS)(Explain)EE 166: Midterm 2 NAME: 3Question 3 (20pts): List all the advantages of CMOS digital Logic. You can use a CMOS inverter as a starting point.EE 166: Midterm 2 NAME: 4Question 4 (15pts): Figure 3 shows different inverters built in the AMI06 um process. (VDD=5V) Four inverters have WN changing from 1.5 microns to 10 microns while WP is the same for each inverter (10 microns). Identify which WP/WN ration produced the left most curve Figure 4. (10pts.) Figure 3: Three different inverters. In this process VDD is 5Volts. Which inverter has the most even noise margins? Figure 4: DC response of three different inverters.EE 166: Midterm 2 NAME: 5Question 5(25pts): Using our process parameters design a CMOS inverter (Driver) to have symmetric propagation delays of .2ns driving a CMOS inverter (Load) with WN=10μm, WP=10μm. Having even noise margins is more important than having a small area. (6pts) Using our process parameters design a CMOS inverter (Driver) to have symmetric propagation delays of .75 ns driving a CMOS inverter (Load) with WN=10μm, WP=10μm. Having even noise margins is more important than having a small area. (6pts) Using our process parameters design a CMOS inverter (Driver) to have symmetric propagation delays of .15ns driving a CMOS inverter (Load) with WN=10μm, WP=10μm. Having a small area and small power is more important that even noise margins. (6pts) Calculate the power of the last inverter you designed if the frequency was 100MHz and the activity factor (α) was equal to one (7pts)EE 166: Midterm 2 NAME: 6Question 6(10pts): Given that the power supply of CMOS digital circuits shrinks with each new generation, to maintain reasonable power densities and limit short channel effects. Write about the impact scaling (shrinking the power supply (VDD)) on the noise margins of CMOS digital


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SJSU EE 166 - Midterm 2

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