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SJSU EE 166 - 4-bit Carry Look Ahead Adder

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4-bit Carry Look Ahead AdderAgendaAbstractIntroductionEquations for Logic of 4-bit CLAPowerPoint PresentationProject SummaryDesign FlowLongest Path CalculationsSchematic: DFFSchematic: Generate and PropagateSchematic: Carry GeneratorSchematic: Sum GeneratorFinal SchematicSchematic TBFinal SimulationFinal LayoutLVS VerificationCost AnalysisLessons LearnedSummaryAcknowledgements14-bit Carry Look Ahead AdderSamira SharmaSuneera SharmaAdvisor: Dave Parent12/6/042Agenda•Abstract•Introduction–Why–Simple Theory•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•We designed an 4-bit carry look ahead adder that operated at 200 MHz and used 16mW of Power and occupied an area of 420x440m24Introduction•Why is a Carry Look Ahead Adder important?-The CLA is used in most ALU designs-It is faster compared to ripple carry logic adders or full adders especially when adding a large number of bits.•The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propage and generate logic to make addition much faster.5C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.C0 Si = Ai  Bi  Ci = Pi Ci. Gi = Ai.Bi Pi = (Ai  Bi) Equations for Logic of 4-bit CLA64-Bit Carry Look Ahead Adder Gate Level Design7Project Summary•We used the gate design methodology instead the AOI design method for Carry logic because of its lesser drain caps we were able to meet timing specifications, also, made hand calculations easier to do.•We used a less complicated design and created separate cells in order make debugging easier and also allow for a neater layout.8Design FlowFunctions andSpecsDesigning For LogicHandCalculationsInitial Sizing Stick DiagramsLayout DRC& ExtractionLVS Post Extraction9Longest Path CalculationsNote: All widths are in micronsand capacitances in fFtPHL = 5ns/11 = 0.45nsLogic Level Gate Cg to Drive NSN NSP N M WN (H.C) WP (H.C) WN (S) WP (S) WN (L) WP (L)1 XOR2 30 2 2 6 6 5.53 9.56 5.55 9. 6 5. 55 9.62 INV 23 1 1 1 1 2.65 4.78 2.65 4.45 2. 65 4.453 OR5 21 1 5 6 10 1.51 10.05 1.5 9 1.5 94 OR4 18 1 4 5 8 1.45 8.02 1.5 8 1.5 85 AND5 12 4 1 8 5 7.81 3.35 7.8 3.35 7.8 3.356 XOR2 10 2 2 6 6 5.36 9.3 5. 8 9. 3 5.8 9.37 AND2 5.5 2 1 4 3 6.82 6.07 6.8 6.07 6.8 6.0710Schematic: DFF11Schematic: Generate and Propagate12Schematic: Carry Generator13Schematic: Sum Generator14Final Schematic15Schematic TB16 Final SimulationA=1B=0Cin=Test Vectors1111+0000 1111 1111100001000017Final Layout18Net-lists match!LVS Verification19Cost Analysis–verifying logic = 10 hours–verifying timing = 20 hours–Layout = 50 hours–post extracted timing = 5 hours20Lessons Learned•Learn the tradeoffs of AOI vs. Gate Design Methodology-Area Constraints-Timing Constraints•Develop Good testing and debugging skills.•Have Fun!21Summary•We met specifications by designing a 4-bit Carry Look Ahead Adder-Rise time= Fall time= 2.65 ns-Total Area= 420x440 m2 -Power= 16 mW•In the future this circuit design can be designed using less power and operating at a higher frequency.22Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to all our classmates that helped us in the lab •Professor David Parent for setting us up for success!•Undo, Stretch, Copy, Move and Metal 1,2 and


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