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SJSU EE 166 - Hamming Code Presentation

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Hamming CodeAgendaAbstractIntroductionLongest PathSchematicSlide 7Slide 8LayoutVerification: DRCVerification: LVSSimulationSlide 13Slide 14Slide 15Cost AnalysisLessons LearnedSummaryAcknowledgements1Hamming Code Clarissa DavidTimmy LauWingChing LinJonathan LeeAdvisor: Dr. David ParentDecember 7, 20052Agenda•Abstract•Introduction–Why a Hamming Code?–Potential Applications–Theory of Operation•Calculations•Cadence Details•Summary of Results•Cost Analysis•Conclusions3Abstract•Target Specification–Clock Frequency: 200MHz–Load Capacitance: 30fF–Area: 900x500 micron squared•Actual Specification–Clock Frequency: 160MHz–Load Capacitance: 30fF–Area: 932.55 x 915.45 micron squared4Introduction•Hamming Code–Detects single and double-bit errors•Application–Telecommunication (i.e. networking)•Theory–Using 4 data bits, can generate 3 correction bits giving a total of 7 bits–Can correct any single bit error5Longest PathCELLBIT#WN Load (cm)WP Load (cm)Cg+Cint tphl (s) WN (cm) WP (cm)NAND2A 1 ? ? 3.0000E-14 2.00E-10 3.80E-04 3.38E-04NAND2B 23.80E-04 3.38E-04 1.2053E-14 1.90E-10 2.22E-04 1.98E-04INVA 32.22E-04 1.98E-04 7.0588E-15 7.50E-11 1.53E-04 2.77E-04INVB 41.53E-04 2.77E-04 7.2093E-15 7.50E-11 1.55E-04 2.81E-04NAND3A 51.55E-04 2.81E-04 7.3253E-15 2.30E-10 3.02E-04 1.78E-04INVC 63.02E-04 1.78E-04 8.0627E-15 8.00E-11 1.52E-04 2.75E-04INVD 71.52E-04 2.75E-04 7.1669E-15 7.50E-11 1.55E-04 2.80E-04NAND2C 81.55E-04 2.80E-04 7.2926E-15 1.20E-10 4.36E-04 3.92E-04INVE 94.36E-04 3.92E-04 1.3902E-14 9.50E-11 1.82E-04 3.28E-04NAND4A 101.82E-04 3.28E-04 8.5568E-15 3.40E-10 3.15E-04 1.50E-04NAND4B 113.15E-04 1.50E-04 7.8037E-15 3.40E-10 3.00E-04 1.50E-04INVF 123.00E-04 1.50E-04 7.5520E-15 7.50E-11 1.61E-04 2.91E-04NAND2D 131.61E-04 2.91E-04 7.5893E-15 1.50E-10 2.50E-04 2.24E-04NAND2E 142.50E-04 2.24E-04 7.9558E-15 1.50E-10 2.50E-04 2.24E-04INVG 152.50E-04 2.24E-04 7.9558E-15 7.50E-11 1.67E-04 3.03E-04NAND4C 161.67E-04 3.03E-04 7.9005E-15 3.40E-10 2.85E-04 1.50E-04NAND3B 172.85E-04 1.50E-04 7.3002E-15 2.10E-10 3.00E-04 1.78E-04INVH 183.00E-04 1.78E-04 8.0177E-15 7.50E-11 1.68E-04 3.05E-046SchematicGate Level Schematic of Hamming CodeNote: This is an Note: This is an Error GeneratorError Generator7SchematicBlock schematic of Hamming without the flip-flop8SchematicSchematic of Hamming Code with flip-flop at the start9LayoutLayout of Hamming Code10Verification: DRCVerification of DRC Passing11Verification: LVSVerification of LVS:Verification of LVS:PASSED!!!!PASSED!!!!12SimulationNCVerilog of Hamming Code Logic13Simulation14SimulationSimulation of Hamming Code with flip-flop15SimulationSimulation of error generator16Cost AnalysisCost AnalysisTask Length of TimeVerifying Logic 1 DayVerifying Timing 1 DayLayout 7 DaysPost Extracted Timing 1 DayTOTAL TIME 10 DaysBut from us….. FREE!!!!!But from us….. FREE!!!!!17Lessons Learned•EXPOSE YOURSELF TO THE PROJECT EARLY•Be organized about your routing•Debugging layout•Work together as a team•EXPOSE YOURSELF TO THE PROJECT EARLY !!!18SummaryComplete CircuitComplete Circuit•Clock Frequency: 160MHz•Area: 932.55 x 915.45 microns squared•Load Capacitance: 30fF19Acknowledgements•Thanks to Cadence Design Systems•Thanks to Professor David Parent •Thanks to the current and past students of


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