Simple FPGAAgendaAbstractIntroductionProject DetailsLUT Schematic AbstractLUT2 Architecture with synchronous clearSwitchSwitch ArchitectureVerificationLongest Path CalculationsSchematicLayoutLVSSimulationsCost AnalysisLessons LearnedSummaryAcknowledgements1Simple FPGA David, Ronald and SudhaAdvisor: Dave Parent12/05/20052Agenda•Abstract•Introduction–Why?–Simple Theory–Back Ground information •Summary of Results•Project Details•Results•Cost Analysis•Conclusions3Abstract•We designed an FPGA with–3 Programmable 2-input Look-up Tables (LUT)–2 Flip Flops–2 Inputs and 2 Outputs•Clock Frequency: up to 242 MHz•Area: slightly under 400x400m2•Power: Still being tested4Introduction•FPGA is a digital circuit that can be “programmed” and “reprogrammed” to behave as different digital circuits.•Four applications that can be implemented in the simple FPGA.–Mod 2 counter (designed and tested)–3 sequential 1’s pattern match detector (designed)–Clock divider (x2) (designed)–1 bit ALU with no carry in (designed)•Why?–Try something different5Project Details•Components:–Two LUTs (Look up Tables)•Five Latches, Four 2X1 MUXs, One Flip Flop per LUT–One LUT2c (Only combinational logic)•Four Latches and One 2X1 MUX per LUT2c–One Interconnection Switch•9 Latches and 9 Transmission Gates•LUT2 architecture:–Latches hold the truth table values –Inputs IN0 and IN1 are the control signals to control the MUX –The output of the LUT can be combinational or registered.6LUT Schematic Abstract QFF2X1In0In1CLKOutRegister SelectProgrammableGate7LUT2 Architecturewith synchronous clear4 x 1FF2IN[1:0]CLKOUTLATCHES012 R2 x 103CLEAR2 x 18Switch•Switch uses the latches to program transmission gates that connects inputs to outputs.9Switch ArchitectureLUT2-A CLRLUT2-A IN1LUT2-A IN0LUT2-A YLUT2-B CLRLUT2-B IN1LUT2-B IN0LUT2-B YLUT2-C IN1LUT2-C IN0LUT2-C YVDDIB-0 IN_XIB-1 IN_X OB-0 OUT_XOB-1 OUT_XTransmission Gate with Control Latchsw_clrsw_in1sw_in010Verification11Longest Path CalculationsnsnsPHL313.165Note: All widths are in microns,capacitances in fF, time in ns.Logic LevelGate Cg to drivephlplh NSN NSP N M R WN WP1 2x1 MUX (INV) 30 1 1 1 1 1.752 1.50 2.632 2x1 MUX (AO) 12 2 2 4 4 1.752 2.72 4.773 INV 18 0.26 0.18 1 1 1 1 1.752 1.50 2.634 TG F02 19 0.11 0.11 1 1 1 1 1.752 1.50 2.635 2x1 MUX (INV) 19 1 1 1 1 1.752 1.50 2.636 2x1 MUX (AO) 12 2 2 4 4 1.752 2.72 4.777 2x1 MUX (INV) 18 1 1 1 1 1.752 1.50 2.638 2x1 MUX (AO) 12 2 2 4 4 1.752 2.72 4.779 INV 20 0.26 0.18 1 1 1 1 1.752 1.50 2.6310 TG FO3 26 0.11 0.11 1 1 1 1 1.752 1.50 2.6311 2x1 MUX (INV) 12 1 1 1 1 1.752 1.50 2.6312 2x1 MUX (AO) 12 2 2 4 4 1.752 2.72 4.77Subtotal 2.87 2.8713SLAVE LATCH NAND30 0.31 0.31 2 1 1 2 0.876 5.71 5.0014SLAVE LATCH MUX18 0.31 0.31 2 2 1 3 1.752 2.35 4.1215MASTER LATCH NAND10 0.31 0.31 2 1 1 2 0.876 2.29 2.0116MASTER LATCH MUX72 0.31 0.31 2 2 2 2 1.752 3.82 6.69Subtotal 1.25 1.25Total 4.12 4.12Spec 5.00 5.000.530.630.530.630.530.630.530.6312Schematic13Layout14LVS15Simulations•We performed worst case SPICE simulations of each gate in the worst case path and summed up.•Worst Case SPICE at top level not done–Time Ran Out!!–SPICE simulation at top level is cumbersome due to need to program FPGA prior to running simulation.16Cost Analysis•Estimate how much time you spent on each phase of the project–verifying logic – 10 hours–verifying timing – 2 hours–Layout – 30 hrs–post extracted timing – 2 hrs17Lessons Learned•Set deadlines for project components to be due and set specs for each project component.•Hold weekly meetings to discuss status/issues and make sure all members are on same page.•Don’t take 124 and 166 in the same semester, not enough time in the day.18Summary•Programming an FPGA was an interesting experience but designing one was exciting.•To learn more about using FPGAs take EE178.19Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software donation even though we didn’t use your software•Thanks to Professor Dave Parent for advice on
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