4 bit Versatile CMOS Rate MultiplierAgendaAbstractIntroductionSlide 5Slide 6Project highlightProject DetailsArchitecture StyleArchitecture StyleSlide 11Longest Path CalculationLongest Path CalculationsSchematicFloor PlanLayoutVerificationSimulation 1Simulation 2Power AnalysisCost AnalysisLessons LearnedSummaryAcknowledgements14 bit Versatile CMOS Rate MultiplierHardik ParikhAkshay BhatAlex JoseSwastick BiswasAdvisor: Dave ParentDATE: 05/11/20052Agenda•Abstract•Introduction–What is a Rate Multiplier and applications–Cumulative adder Principle–Improvements made to make the circuit versatile •Project Highlight•Project Details•Results•Cost Analysis•Conclusion3Abstract We designed a 4-bit rate multiplier that operates at 200 MHz and uses 18.9mW of Power and occupies an area of 380 x 200 m24Introduction•Rate Multiplier: A digital circuit that multiplies the incoming clock by a ratio to give an output pulse rate:where,P and Q are integers and P < QThis is not a frequency divider as numerator P is not one•Application: * Arithmetic & Mathematic Functional generation* PCM systems* Motor Control Systems * Vector Generation & Interpolation * Frequency Synthesizer (clock)QP out rate 5IntroductionD RegisterD RegisterFull AdderCapacity = QFull AdderCapacity = QPClockReset PQ(Clock)Cumulative Adder Principle6Introduction4 bit D Register4 bit D Register4 bit Adder (CLA)4 bit Adder (CLA)PClockReset PQ(Clock)4 bit Multiplexer (2:1)4 bit Multiplexer (2:1)Adder (CLA)Adder (CLA)1’s Complement 1’s Complement QCin = 1D24 – Q + Pselectc_out7Project highlight•Programmable rates that broaden the application area considerably• High speed implementation through Carry look ahead adders•Optimally spaced output pulse distribution•Cascadable in multipliers of 4 bits•Most of the standard industry chips are BCD rate multipliers. This rate multiplier is more versatile as the denominator Q is programmable.8Project DetailsFunctional VerificationArchitecture StyleFloor PlanningSizing, Schematics,SimulationPost extraction simulationLayout & Verification9Architecture Style Option 1: Standard AOI10Architecture StyleOption 2:Using minimum transistorsExample: Carry outc4 = G3 + P3G2 +P3P2G1 + P3P2P1G0+ P3P2P1P0C011Architecture StyleOption 3: Combination ofAOI and Boolean Gates.12Longest Path Calculation4 bit D Register4 bit D Register4 bit Adder (CLA)4 bit Adder (CLA)PClockReset PQ(Clock)4 bit Multiplexer (2:1)4 bit Multiplexer (2:1)Adder (CLA)Adder (CLA)1’s Complement 1’s Complement QCin = 1DAssuming that P andQ do not change13Longest Path CalculationsLogic BlockLogic Level CELL WN Load WP LoadCg of load Cg+Cint tphl/tplhNSNNSP N M WN WPCLA1NAND3_C4 2. 50E-14 3. 00E-14 3. 00E-10 3 1 5 3 7. 41E-04 4. 34E-042AOI_C47. 41E-04 4. 34E-04 1. 97E-14 2. 47E-14 7. 50E-10 3 3 9 9 3. 56E-04 5. 86E-04MUX3INV2. 14E-04 1. 89E-04 6. 77E-15 4. 99E-04 8. 45E-04 2. 26E-14 2. 93E-14 3. 93E-14 1. 50E-10 1 1 1 1 2. 47E-04 4. 43E-044MUX_AOI2. 47E-04 4. 43E-04 1. 16E-14 1. 66E-14 3. 00E-10 2 2 4 3 2. 69E-04 4. 72E-045INV_SELECT2. 69E-04 4. 72E-04 4. 98E-14 6. 98E-14 1. 50E-10 1 1 1 1 4. 28E-04 7. 67E-04DFF6SLAVE_INV4. 28E-04 7. 67E-04 2. 01E-14 2. 69E-04 4. 72E-04 1. 24E-14 3. 25E-14 4. 25E-14 2. 30E-10 1 1 1 1 4. 52E-04 8. 01E-047SLAVE_AOI_4. 52E-04 8. 01E-04 2. 10E-14 2. 60E-14 4. 30E-10 3 2 6 5 6. 46E-04 7. 42E-048MASTER_INV6. 46E-04 7. 42E-04 2. 33E-14 2. 83E-14 2. 30E-10 1 1 1 1 3. 09E-04 5. 47E-049MASTER_AOI3. 09E-045. 47E-04 1. 44E-14 1. 94E-14 4. 30E-10 3 2 6 5 5. 34E-04 6. 14E-04TP = 5 nsec / 9 = 0.555 n sec14Schematic15And D ff(input) D ff(input) D ff(input) D ff(input) CLA 1 CLA 1 CLA 1 Mux Mux Mux CLA 1 Mux CLA 2 CLA 2 CLA 2 CLA 2 D ff(input) D ff(input) D ff(Register) D ff(Register) D ff(input) D ff(input) D ff(Register) D ff (Register) D ff(Sync.)Floor Plan16LayoutFeatures: Vdd and Ground lines interleaved to save area Efficient routing and negligible empty space Approximately squarish. The 4 hours spent on floor planning was worth it!17Verificationnet-lists match !18Simulation 119Simulation 220Power Analysis21Cost Analysis•Time spent on each phase of the project in man hours–Verifying logic: 10 –Schematic, sizing and verifying timing: 40–Layout: 140–Post extracted timing: 522Lessons Learned•Have a rough idea of DRC rules before sizing the transistors. We underestimated the DRC minimum metal spacing only to find that the design became too tight. •Before starting layout spend time on making a floor plan •Document your design•Using Cell based design makes life easy! It reduces debug time•Time management is the key between success and failure!23Summary•This project gave us a good overview of Digital CMOS Circuit Design. •Rate-multipliers can be used for low power frequency synthesizers.24Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Professor Dr. Parent for his timely
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