DESIGN OF 8-BIT ALUAgendaAbstractIntroductionDesign FlowProject SummaryPowerPoint PresentationSlide 8SchematicSlide 10Slide 11Simulation (Arithmetic operations)LayoutVerificationSlide 15Slide 16ResultsConclusionsLessons LearnedAcknowledgements1DESIGN OF 8-BIT ALUVijigish LellaHarish GogineniBangar Raju SingarajuAdvisor: Dr. David W. Parent8 May 20062Agenda•Abstract•Introduction•Summary of Results•Project (Experimental) Details•Results•Conclusions3Abstract•The Aim of the project is to design a 8-bit ALU.•The circuit is designed so as to meet the following specifications: –Frequency: 200 MHz.–Power : 100 mW. –Area : 576x840 µm2•The design was done in AMI06 technology using Cadence tools.4IntroductionWhy this project?•The ALU is a fundamental building block of any computing system.•Challenging to design a 18 logic level design using CMOS Technology.•Design consists of different kinds of logic… Brent-Kung Adder, DFF, AOI3333, Mux, Inv, Nand, Nor, Xor, etc.5Design FlowSelection of Adder Timing and PowerAnalysisCalculations for theCritical PathGate level DesignFunctional TableNC VerilogVerificationDRC & LVS for each bitLayout of Individual cellsSchematic of Individual cells Final DRC & LVSIntegration of bits6Project Summary•The ALU performs 1 Arithmetic function and 9 Logical functions at 200MHz.•Uses Brent Kung Adder to perform addition.•Design uses maximum power of 100mW•Maximum area is 576 x 840µm2789Schematic100 1 1 0 0 0 0 10 1 1 0 0 0 0 00 0 0 1 0 0 0 00 1 1 1 0 0 0 01 1 0 0 0 0 0 01 1 1 0 0 0 0 00 0 0 0 0 0 0 00 1 1 1 0 0 0 01 0 0 0 0 0 0 01 0 0 1 0 0 0 0ADDAxorBABA+BAINVBINVGenerateC1 C2 C3 C4 C5 C6 C7 C8 PropagateNANDMORNORXNOR11Longest Path CalculationsTotal Propagation delay for the longest path = 3.72nsINVAOI22INVAOI22XOR2INVINVAOI21INVNAND2INVNAND2INVNAND2INVNAND2INVAOI33331.90E-151.90E-151.90E-152.60E-152.70E-152.70E-153.50E-153.60E-154.00E-154.50E-155.50E-156.00E-156.50E-151.05E-141.10E-141.65E-141.70E-142.00E-142.0000E-142.1026E-142.2390E-144.6206E-144.2092E-142.2826E-144.2877E-142.4171E-143.9861E-142.2583E-144.7082E-144.1353E-145.7941E-144.5035E-145.6127E-144.6848E-145.7171E-144.2571E-147.00E-112.80E-107.00E-113.50E-103.30E-107.50E-119.90E-112.50E-101.00E-101.20E-101.20E-101.40E-101.30E-101.55E-101.30E-101.65E-101.50E-109.90E-101 1 1 1 1.8132 2 3 4 1.7601 1 1 1 1.8132 2 3 4 1.7432 2 3 4 1.7481 1 1 1 1.8111 1 1 1 1.8052 2 2 3 1.7681 1 1 1 1.8052 1 2 1 0.9001 1 1 1 1.8002 1 2 1 0.8981 1 1 1 1.7982 1 2 1 0.8961 1 1 1 1.7982 1 2 1 0.8941 1 1 1 1.793 1.5834.45E-04 8.07E-044.83E-04 8.51E-044.89E-04 8.87E-044.57E-04 7.97E-044.95E-04 8.65E-044.54E-04 8.23E-045.13E-04 9.27E-044.29E-04 7.58E-044.80E-04 8.66E-047.38E-04 6.64E-044.40E-04 7.92E-049.10E-04 8.17E-044.80E-04 8.62E-048.82E-04 7.90E-044.99E-04 8.97E-048.99E-04 8.04E-044.54E-04 8.14E-046.12E-04 9.69E-04GATE C int Cg Tphl Nsn Nsp N M R Wn WpF F s cm cm12Simulation (Arithmetic operations)13Layout DFFINPUTOUTPUT14Verification151617Results•The ALU performs all 10 functions at a 200MHz clock and a load of 20fF.•Area of the layout is 576 x 840µm218Conclusions•Designed a 8-Bit ALU that performs arithmetic and logical functions at 200MHz frequency driving up to 20fF.•The Logic design can be modified to perform more functions.19Lessons Learned•Cell based design•Uniform cell height•Floor planning•Grid pattern for Vdd and gnd•Debugging LVS errors using extracted view20Acknowledgements•Thanks to Professor David W. Parent for his guidance.•Thanks to Cadence Design Systems for the VLSI
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