Modular Arithmetic Logic UnitAgendaAbstractPowerPoint PresentationIntroductionSlide 6Previous WorkProject SummaryProject DetailsLongest Path CalculationsSchematicSlide 12Slide 13LayoutSlide 15VerificationSlide 17Slide 18SimulationsSlide 20Slide 21Cost AnalysisLessons LearnedSummaryAcknowledgements1Modular Arithmetic Logic UnitBy Salvador Sandoval & Lucas MoralesAdvisor: Dave ParentDecember 6, 20042Agenda•Abstract•Introduction–Reasons for selecting 4-bit ALU design–Overview of ALU design•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•A modular Arithmetic Logic Unit was designed to operate at 200 MHz and to use less than 23W/cm2 of power and occupy an area of less than 800 x 800 m2. The modular ALU design will be demonstrated with a 4-bit ALU.4•To design an ALU circuit that can be used for an arbitrary number of bits.•To design an n-bit ALU in a hierarchical top-down fashion. Use top-down design methodology by decomposing the ALU into one-bit slices, where slice i performs the desired functions on bits ai and bi of the operands and produces the result bit fi.IntroductionB = (bn-1…b0) A = (an-1…a0)Y = (yn-1…y0)S = (sn-1…s0)ALUOPERANDSSELECTRESULT5IntroductionS0S1S2C-GenC-1ALUOUT_0A0B0C0ALUOUT_2A1B1C1ALUOUT_2A2B2C2ALUOUT_iAiBiCi Ci-1•Each ALU block will perform the desired functions on bits ai and bi.6IntroductionTable 1. ALU Function Table ALU Block DiagramSelection Code ALU S2 S1 S0 Function Description 0 0 0 F = A + B Add 0 0 1 F = A - B Subtract 0 1 0 F = A + 1 Increment 0 1 1 F = A - 1 Decrement 1 0 0 F = A & B AND 1 0 1 F = A OR B OR 1 1 0 F = A Not 1 1 1 F = A B XORMUXOUT_iS0S1S2ALULUOUT_LUAiBiAUOUT_AUAiBiCi7Previous Work•Previous ALU designs were designed for specific bit widths and therefore reduced design flexibility.•The modular approach in our design will enable a single ALU block to be expanded for n-bits.8Project Summary•Top level ALU was decomposed into smaller modules. The smaller modules were subsequently decomposed until the entire design was represented by an interconnection of small functional modules.•The ALU modules can be cascaded to create an n-bit ALU. Therefore, allowing greater reusability and flexibility.9Project Details•Results of design–Layout:•Operating Frequency 178.5 MHz•Power: 13.36 W/cm2•Area: 1.75 x10-3 cm2•Fully Operational–Schematic: •Operating Frequency 200MHz•Power: 20.61 mW/cycle•Fully Operational10Longest Path CalculationsnsnsPHL67.26154nsnsPHL5.21Combinational Logic Delay Flip-Flop Logic Delay11SchematicArithmetic Logic Unit12SchematicArithmetic Unit13SchematicLogic Unit14LayoutArithmetic Logic Unit15LayoutArithmetic Logic Unit with DFF’s16Verification17VerificationPower = 124.098 mW/ 6-CyclesPower = 11.76W/cm2Area = 1.75 x10-3 cm2Arithmetic Logic Unit Schematic18VerificationPower = 70.126 mW/ 3-CyclesPower = 13.36W/cm2Area = 1.75 x10-3 cm2Arithmetic Logic Unit Layout19Add OperationSimulations20SimulationsXOR Operation21SimulationsSubtract Operation22Cost Analysis•Time spent to project–Verifying logic = 3 hrs.–Verifying timing = 16 hrs.–Layout = 40 hrs.–Post extracted timing = 8hrs.23Lessons Learned•Take interconnect capacitance into account when designing and laying-out a circuit.24Summary•We designed a functional modular Arithmetic Logic Unit circuit.•Failed to meet post extracted timing because we overlooked a few items (i.e.: interconnect capacitance, signal buffers, and signal routing)•We will definitely take these items into account on future designs.25Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software
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