Serial MultiplierAgendaAbstractIntroductionPowerPoint PresentationProject DetailsLongest Path CalculationsOne Bit SchematicSchematicVerilog TestbenchSlide 11LayoutVerificationSimulationsCost AnalysisLessons LearnedSummaryAcknowledgements1Serial MultiplierAnn ZhouYing YanWei LiangAdvisor: David ParentMay 17th, 20042Agenda•Abstract•Introduction–Why–Simple Theory–Back Ground information (Lit Review)•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3AbstractWe designed a 5-bit serial multiplier that operated at 200 MHz and used 3.8W/cm2 of Power and occupied an area of 767x189m2 3.8W/cm2, no cooling is needed4IntroductionAdvantages over equivalent parallel multiplier•Huge reduction in the required hardwarein applications where high data rates are not necessary•Reduce input and output routing5Serial multiplier schematic6Project Details•Hand calculations for the longest path •Final schematic •Verilog Waveform and Testbench•Final layout•Verification (DRC and LVS)•Final simulation (post extracted)7Longest Path CalculationsnsnsPHL4545.115Note: All widths are in micronsand capacitances in fFLogicLevelGate Cg toDrive#CDNs#CDPs #LNs #LPs WN(H.C)WP(H.C)Cg of gate1 DFF-NAND3 30 5 3 3 1 5.16 2.96 15.142 DFF-NAND2 15.14 3 2 2 1 1.5 1.5 5.13 DFF-INV 5.1 1 1 1 1 1.5 2.567 6.954 XOR2-AOI 6.95 6 6 2 2 1.68 2.796 7.625 XOR2-INV 7.62 1 1 1 1 1.5 2.567 6.956 XOR2-AOI 6.95 6 6 2 2 1.68 2.796 7.627 XOR2-INV 7.62 1 1 1 1 1.5 2.567 6.958 AND2-INV 17.15 1 1 1 1 1.5 2.567 6.959 AND2-AOI 6.95 3 2 2 1 1.5 1.5 5.1010 LATCH-NAND2 5.10 3 2 2 1 1.5 1.5 5.1011 LATCH-AOI 5.10 3 3 2 2 1.5 2.224 6.348One Bit Schematic9Schematic10Verilog Testbench11Verilog waveform12Layout13Verification14Simulations15Cost Analysis•Estimate the time we spent on each phase of the project–verifying logic (four weeks)–verifying timing (one week)–layout (two weeks)–post extracted timing (one week)16Lessons Learned•Verify the logic of the design before layout•Plan the cell height •Avoid using metal3 to route power and ground17Summary•We designed a 5-bit serial multiplier that operated at 200 MHz and used 3.8W/cm2 of Power and occupied an area of 767x189m2•Compared with equivalent parallel multiplier, our design saved a lot of hardware and area in applications not requiring very high data rates.18Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software donation•Thanks to Professor D.Parent•Thanks to our EE166
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