4-Bit ALUHighlightsCircuit FunctionalityBlock Diagram for 4-Bit ALUDesign FlowAND2 schematicAND2 Layout & LVS ReportOR2 SchematicOR2 Layout & LVS ReportXOR2 SchematicXOR2 Layout & LVSFull Adder SchematicFull Adder LayoutFull Adder LVS Report4-to-1 MUX schematic4-to-1 MUX schematic (cont.)4-to-1 MUX Layout4-to-1 MUX LVS Report1-bit ALU schematic1-bit ALU Layout1-bit ALU LVS Report4-bit ALU Schematic4-bit ALU Layout4-bit ALU LVS ReportTest VectorsSimulation ResultsSlide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Simulation Results (Cout)Simulation Results (Cin)Propagation Delay for AND gatePropagation Delay for OR gatePropagation Delay for XOR gatePropagation Delay for Full AdderPropagation Delay for 4-to-1 MUXPropagation Delay For 4-bit ALU (when S1=S0=0 AND Operation)Propagation delay For 4-bit ALU ( when S1=0, S0=1 OR Operation)Propagation Delay for 4-bit ALU (when S1=1, S0=0 XOR Operation)Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)Slide 45Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)Power Simulation for 4-bit ALU (when S1=S0=0 AND Operation)Power Simulation For 4-bit ALU ( when S1=0, S0=1 OR Operation)Power Simulation for 4-bit ALU (when S1=1, S0=0 XOR Operation)Power Simulation for 4-bit ALU (when S1=S0=1 Add Operation)Conclusions1Specifications Functionality: AND, OR , XOR, ADDMaximum propagation delay : 2nsPower budget: 30mWArea: 200 µm ×400µmPrepared by: Christie Ma, Manjul Mishra, Ka YungPresented to : Dr. David ParentDate: 7th May, 20034-Bit ALU4-Bit ALU2HighlightsHighlights•Introduction- How does the circuit work•Approach for the design•Individual blocks – AND gate, OR gate, XOR gate, Full Adder, and 4-to-1 MUX•Wiring of 1-bit and 4-bit ALU•Verification of functionality – test vectors •Post extracted simulation with propagation delay•Power consumption •Conclusions3Circuit FunctionalityCircuit FunctionalityA0B04:1MUXF0Cout0S1S0ADDA0B0A0B0A0B0C0Control signal S1 S0Operation0 0 A and B0 1 A or B1 0 A xor B1 1 A add BBlock diagram for 1-bit ALU4Block Diagram for 4-Bit ALUBlock Diagram for 4-Bit ALU1-bit ALU1-bit ALU1-bit ALU1-bit ALUA0B0C0A1B1A2B2A3B3F0F1F2F3Cout0Cout1Cout2 S1 S0Cout35Design FlowDesign FlowCalculate Wn Wp for each blockRun Spice simulation to fix Wn, WpDraw schematic for each blockLayout for small blocksRun DRC, LVS, extracted simulation for small blocksRoute small blocks together to form 1-bit ALURoute four 1-bit ALUs to form a 4-bit ALURun DRC, LVS, extracted simulation for 4-bit ALUVerify functionality Measure delay timeMeasure power usedSketch schematic according to Boolean AlgebraFind Euler PathDraw stick diagramRun DRC, LVS, extracted simulation for 1-bit ALU6AND2 schematicAND2 schematicWp=5.4 mWn=15.15 m7AND2 Layout & LVS ReportAND2 Layout & LVS Report8OR2 SchematicOR2 SchematicWp=8.4mWp=5.85 mWn=10.2 m Wn=14.25 m9OR2 Layout & LVS ReportOR2 Layout & LVS Report10XOR2 SchematicXOR2 Schematic Y = A xor B = AB’ + A’B = (AB + A’B’)’ AOI21 = (AB + C)’if C = A’B’ C = (A+B)’ C = A nor B Therefore, using one AOI21 and one NOR gate, we can implement XOR gate without using any INV. Wp=15.9mWn=23.4m11XOR2 Layout & LVS12Full Adder SchematicWp=6.15mWn=3.6mCout=AB+ACin+ BCin = AB+Cin(A+B)Sum= ABCin + (A+B+Cin)Cout’13Full Adder Layout14Full Adder LVS Report154-to-1 MUX schematicF0= S0’(S1’Y00+S1Y10)+S0(S1’Y01+S1Y11) 2-to-1 MUX 2-to-1 MUX2-to-1 MUXWp=9.9 mWn=6.45 mTherefore, we need three 2-to-1MUXsto build a 4-to-1 MUXF0= S1’ S0’Y00+ S1’S0Y01 +S1S0’Y10+S1S0Y112-to-1 MUX schematic164-to-1 MUX schematic (cont.)174-to-1 MUX LayoutOne 2-to-1 MUXThree 2-to-1 MUXs to form a 4-to-1MUX3184-to-1 MUX LVS Report191-bit ALU schematic201-bit ALU LayoutANDXORORADDER4-to-1 MUX211-bit ALU LVS Report224-bit ALU Schematic234-bit ALU LayoutArea = 197m  347.4 m244-bit ALU LVS Report25Test VectorsTest Vectors•Walking ones for inputs on all operations (1-8)•Testing for Cout and Cin (9, 10)26Simulation ResultsSimulation ResultsA3 = 1, Ax = 0, Bx = 027Simulation ResultsSimulation ResultsA2 = 1, Ax = 0, Bx = 028Simulation ResultsSimulation ResultsA1 = 1, Ax = 0, Bx = 029Simulation ResultsSimulation ResultsA0 = 1, Ax = 0, Bx = 030Simulation ResultsSimulation ResultsB3 = 1, Ax = 0, Bx = 031Simulation ResultsSimulation ResultsB2 = 1, Ax = 0, Bx = 032Simulation ResultsSimulation ResultsB1 = 1, Ax = 0, Bx = 033Simulation ResultsSimulation ResultsB0 = 1, Ax = 0, Bx = 034Simulation Results (Cout)Simulation Results (Cout)A3 = 1, B3 = 135Simulation Results (Cin)Simulation Results (Cin)C0 = 1, A0 =1, B0 =136Propagation Delay for AND gatePropagation Delay for AND gate274.1ps37Propagation Delay for OR gatePropagation Delay for OR gate237.9 ps38Propagation Delay for XOR gatePropagation Delay for XOR gate226.7ps39Propagation Delay for Full AdderPropagation Delay for Full Adder495.5 ps40Propagation Delay for 4-to-1 MUXPropagation Delay for 4-to-1 MUX330.4 ps41Propagation Delay For 4-bit ALU Propagation Delay For 4-bit ALU (when S1=S0=0 (when S1=S0=0 AND Operation)AND Operation)t F2 = 705.9ps t F3 = 698.2ps42Propagation delay For 4-bit ALUPropagation delay For 4-bit ALU ( when S1=0, S0=1 OR Operation)( when S1=0, S0=1 OR Operation)t F2 = 693.8 pst F3 = 673.2 ps43Propagation Delay for 4-bit ALUPropagation Delay for 4-bit ALU(when S1=1, S0=0 XOR Operation)(when S1=1, S0=0 XOR Operation)t F2 = 661.2 pst F3 = 678.7 ps44Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)t F0 = 987.9 pst F1 = 1.383 ns45Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)t F2= 1.484 nst F3 = 1.949 ns46Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)t Cout3 = 1.339 ns47Power Simulation for 4-bit ALU Power Simulation for 4-bit ALU (when S1=S0=0 AND Operation)(when S1=S0=0 AND Operation)Power = 26.8 mW48Power Simulation For 4-bit ALUPower Simulation For 4-bit ALU ( when S1=0, S0=1 OR Operation)( when S1=0, S0=1 OR Operation)Power = 26.69 mW49Power Simulation for 4-bit ALUPower Simulation for 4-bit ALU(when S1=1, S0=0 XOR Operation)(when S1=1, S0=0 XOR Operation)Power =21.38mW50Power