Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 140 60 80 100 120406080mm5. CMOS Gate CharacteristicsJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M-ICS – VLSI ISpring 2012January 13-14, 2012ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 1 / 3540 60 80 100 120406080mmTopicsDC ResponseLogic Levels and Noise MarginsTransient ResponseDelay EstimationECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 1 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 240 60 80 100 120406080mmTransistor BehaviorBehavior in different situations (increase, decrease, or notchange).1If the width of a transistor increases, the current will2If the length of a transistor increases, the current will3If the supply voltage of a chip increases, the maximumtransistor current will4If the width of a transistor increases, its gate capacitance will5If the length of a transistor increases, its gate capacitance will6If the supply voltage of a chip increases, the gate capacitanceof each transistor willECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 2 / 3540 60 80 100 120406080mmTransistor BehaviorBehavior in different situations (increase, decrease, or notchange).1If the width of a transistor increases, the current will increase2If the length of a transistor increases, the current willdecrease3If the supply voltage of a chip increases, the maximumtransistor current will increase4If the width of a transistor increases, its gate capacitance willincrease5If the length of a transistor increases, its gate capacitance willincrease6If the supply voltage of a chip increases, the gate capacitanceof each transistor will not changeECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 3 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 340 60 80 100 120406080mmDC Response: Voutvs. Vinfor a GateStudy the response of InvertersWhen Vin= 0 =⇒ Vout= VDDWhen Vin= VDD=⇒ Vout= 0In between, Voutdepends ontransistor size and currentBy KCL, current must be such thatIdsn= |Idsp|We could solve equations, butgraphical solution gives moreinsightECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 4 / 3540 60 80 100 120406080mmTransistor OperationCurrent through transistor depends on the region of operationNeed to identify for what Vinand Voutare nMOS and pMOSin Cutoff, Linear or SaturationnMOS OperationCutoff Linear SaturatedVgsn< VtnVgsn> VtnVgsn> VtnVin< VtnVin> VtnVin> VtnVdsn< Vgsn− VtnVdsn> Vgsn− VtnVout< Vin− VtnVout> Vin− VtnVgsn= VinVdsn= VoutECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 5 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 440 60 80 100 120406080mmpMOS OperationCutoff Linear SaturatedVgsp> VtpVgsp< VtpVgsp< VtpVin> VDD+ VtpVin< VDD+ VtpVin< VDD+ VtpVdsp> Vgsp− VtpVdsp< Vgsp− VtpVout> Vin− VtpVout< Vin− VtpVgsp= Vin− VDDVdsp= Vout− VDDVtp< 0ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 6 / 3540 60 80 100 120406080mmI-V CharacteristicsMake pMOS wider than nMOS such that βn= βpβ = µCoxWLECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 7 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 540 60 80 100 120406080mmCurrent vs. Vout, VinECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 8 / 3540 60 80 100 120406080mmLoad Line AnalysisTo find the Voutfor a given VinFor a given Vin, plot Idsn, Idspvs. VoutVoutmust be where |currents| are equal in the graph belowECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 9 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 640 60 80 100 120406080mmDC Transfer CurveTranscribe points on to Vinvs. VoutplotECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 10 / 3540 60 80 100 120406080mmOperating RegionsRevisit transistor operating regionsRegion nMOS pMOSA Cutoff LinearB Saturation LinearC Saturation SaturationD Linear SaturationE Linear CutoffECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 11 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 740 60 80 100 120406080mmBeta RatioIf βp/βn6= 1,switching point willmove from VDD/2Called skewed gateAnalysis of more complex gatesCollapse into equivalent inverterECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 12 / 3540 60 80 100 120406080mmNoise MarginsHow much noise can a gate input see before it does not recognizethe input?ECE Department, University of Texas at Austin Lecture 5. CMOS Gate Characteristics J. A. Abraham, January 13-14, 2012 13 / 35Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, January 13-14Introduction to VLSI Design, VLSI I–ICS, Spring 20125. CMOS Gate Characteristics 840 60 80 100 120406080mmLogic LevelsTo maximize noise marginsSelect logic levels at unity gain point of DC transfercharacteristicECE Department,