Adnan Aziz EE 382M – Synthesis of Digital SystemsEmail: [email protected] Spring 2007ACES 6.120 Unique No: 16525Office Hours: MW 10:00-11:00am — ACE 6.120 Lecture: MW 11:00-12:30pm — ENS116Description:This course aims to study the use of computers to automate the process of digital design, specificallythe problem of design synthesis.We will begin by reviewing the basic definitions of Boolean logic and digital systems, continued byan in-depth study of optimization techniques for PLAs and general combinational logic.This will be followed by a survey level treatment of a number of topics in logic synthesis, includinglogic fault testing, technology mapping, timing analysis, performance optimization, and synthesis forlow-power.Afterwards, we will focus on sequential designs. Specifically, representational issues, flexibility avail-able for synthesis, state assignment and minimization, retiming, and FSM verification will be covered.Prerequisites:This course is intended for graduate students with a knowledge of digital design and C programming,and a reasonable degree of mathematical sophistication.Recommended texts:1. S. Hassoun, T. Sasao, and R.K. Brayton, “Logic Synthesis and Verification”, Kluwer AcademicPublishers, 2001.2. G.D. Hachtel and F. Somenzi, “Logic Synthesis and Verification Algorithms”, Kluwer AcademicPublishers, 1996.3. Giovanni de Micheli, “Synthesis and Optimization of Digital Systems”, McGraw Hill, 1994.Format/Evaluation:Approximately 8 homeworks will be assigned; these will range from devising algorithms to designand synthesis, and will be worth 30% of your grade. There will be two midterms worth a combined35% of your grade; a substantial final project will constitute the remainder of the grade.Where does this course fit in?In conjunction with this course, you might consider taking: VLSI-1 this is a foundations graduatecourse; Computer Architecture; and/or CAD for ICs. After taking this course you might considertaking, Verification of Digital Systems, Fault Tolerant Computing; and/or Digital Systems Simulation.Web site: All material related to the course is available athttp://www.ece.utexas.edu/˜adnan/syn-07Tentative ScheduleMaterial1.17 Role of synthesis in VLSI DesignBoolean functions1.22 Representations1.24 BDDs2-level Logic Minimization1.29 BDDs1.31 Exact 2-level minimization — Quine-McKluskey2.5 Heuristic minimization: ESPRESSO2.5 Heuristic minimization: ESPRESSOMulti-level logic minimization2.7 Multi-level logic: definitions2.12 Factoring, substitution, elimination2.14 Factoring, substitution, elimination2.19 Don’t cares and node simplification2.21 Don’t cares and node simplification2.26 Technology mapping for area2.28 Technology mapping for area3.5 Project descriptions & midterm review3.7 Midterm 1Timing3.19 Technology mapping for performance3.21 ATPG3.26 Timing analysis – 13.28 Timing optimization – 24.2 Timing optmization – 14.4 Timing optimization – 2Sequential Logic Synthesis4.9 Representations4.11 State minimization4.16 Retiming – 14.18 Retiming – 2Low power design4.23 Low power – 14.25 Low power – 24.30 Midterm 25.2 Review/Guest LectureNOTE: All departmental, college and university regulations concerning drops will befollowed. The University of Texas at Austin provides upon request appropriate aca-demic adjustments for qualified students with disabilities. For more information, con-tact the Office of the Dean of Students at 471-6259, 471-4241