Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 140 60 80 100 120406080mm2: Transistors, Fabrication, LayoutJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M.7 – VLSI IFall 2011August 29, 2011ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 1 / 4340 60 80 100 120406080mmConductivity in Silicon LatticeLook at the behavior of crystalline siliconAt temperatures close to 0 K, electrons in outermost shelltightly bound (insulator)At higher temps., (300 K), some electrons have thermalenergy to break covalent bondsECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 1 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 240 60 80 100 120406080mmThe Elements (Periodic Table)ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 2 / 4340 60 80 100 120406080mmBuild Systems with Information on ElectricalCharacteristics of Building Blocks (Transistors)This course will not cover semiconductor physicsLearn this from other courses in the departmentWe will design VLSI circuits knowing the electrical behavior ofthe transistorsECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 3 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 340 60 80 100 120406080mmDopantsUsed to selectively change the conductivity of siliconSilicon is a semiconductorPure silicon has no free carriers and conducts poorlyAdding dopants impurities to pure silicon increases theconductivityGroup V: extra electron (n-type)Group III: missing electron, called hole (p-type)ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 4 / 4340 60 80 100 120406080mmp-n JunctionsDiodesA junction between p-type and n-type semiconductor forms adiodeCurrent flows only in one directionECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 5 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 440 60 80 100 120406080mmp-n Junction, Cont’dSource: Prof. Dr. Helmut F¨oll, University of KielECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 6 / 4340 60 80 100 120406080mmnMOS TransistorFour-Terminal device: gate, source, drain, bodyGate oxide body stack looks like a capacitorGate and body are conductorsSiO2 (oxide) is a very good insulatorCalled metal oxide semiconductor (MOS) capacitor, eventhough gate material changed to polysiliconRecent gate material in nanoscale processes is back to metalECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 7 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 540 60 80 100 120406080mmnMOS Transistor OperationBody (bulk) is commonly tied to Ground (0 V)When the gate is at a low voltageP-type body is at low voltageSource-body and drain-body diodes are OFFNo current flows, transistor is OFFWhen the gate is at a high voltagePositive charge on gate of MOScapacitorNegative charge attracted to bodyInverts a channel under gate to n-typeNow electrons can flow through n-typesilicon from source through channel todrain, transistor is ONECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 8 / 4340 60 80 100 120406080mmpMOS TransistorSimilar to nMOS transistor, but doping and voltages reversedBody tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFBubble indicates inverted behaviorECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 9 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 640 60 80 100 120406080mmCMOS FabricationSilicon technologyCMOS transistors are fabricated on silicon waferLithography process similar to printing pressOn each step, different materials are deposited or etchedEasiest to understand by viewing both top and cross-sectionof wafer in a simplified manufacturing processExample inverter cross-sectionTypically use p-type substrate for nMOS transistorsRequires n-well for body of pMOS transistorsn+p substratep+n wellAYGNDVDDn+p+SiO2n+ diffusionp+ diffusionpolysiliconmetal1nMOS transistor pMOS transistorECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 10 / 4340 60 80 100 120406080mmWell and Substrate TapsSubstrate contacts are critical to correct operation of CMOSSubstrate must be tied to GND, n-well to VDD(reverse-biased diodes isolate regions)Metal to lightly-doped semiconductor forms poor connectioncalled Schottky Diode – use heavily doped well and substratecontacts/tapsn+p substratep+n wellAYGNDVDDn+p+substrate tap well tapn+ p+ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 11 / 43Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, August 29, 2011Introduction to VLSI Design, VLSI I, Fall 20112. Transistors, Fabrication, Layout 740 60 80 100 120406080mmInverter MasksTransistors and wires are defined by masksCross-sections shown above taken along dashed lineECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 29, 2011 12 / 4340 60 80 100 120406080mmExamples of Fabrication StepsStart with blank waferBuild inverter from the bottom upFirst step is to form