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UT EE 382M - EE 382M Exam 1

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1EE382M-ECD, VLSI I J. AbrahamSpring 2009 EXAM. I March 14, 2009Name: Student, A• Open Book, Open Notes.• Time Limit: 75 minutes (pace yourself).• Check for 5 pages in exam.• Write all your answers in the spaces/boxes provided.• Show any calculations in these pages using the back of the pages if needed.• State clearly any assumptions made.1. (15 points)Size the transistors in the following c ircuit so that it has the same drive strength(current), in the worst case, as an inverter with p-channel width of 3 and an n-channel width of 2 units. Use the smallest integer widths to achieve this ratio.Write down the size next to each transistor.22. (15 points)Assume an initial voltage of 0.5V on all the internal nodes in the circuits below.Assuming Vtn= 0.2V and |Vtp| = 0.2V , and given the voltages on the gates and nodeA, write down the voltages on nodes B, C, D and E (next to the nodes).111 0.90.9AB CED10.910.91A BC DE0000.10.1AB C D E00.1 00.10ACB DE33. (25 points)Use the Elmore delay approximation to find the worst-case rise and fall delays atthe output for the following circuit. The gate sizes of the transistors are given inthe figure. Use the assumption that the diffusion capacitance is equal to the gatecapacitance, and that a minimum sized transistor has gate and diffusion capacitanceequal to C. The resistance of an nMOS transistor with unit width is R and theresistance of a pMOS transistor with width 2 is also R. Also assume NO sharingof diffusion regions. (Hint: off-path capacitances can contribute to delay.)abcdeeacdb3626663323Input for worst-case rise delay (abcde) =Worst-case rise delay =Input for worst-case fall delay (abcde) =Worst-case fall delay =44. (15 points)Find the logical efforts for the inputs, a, b, c, d and e in the circuit below.abcdeeacdb3626663323Logical effort of a =Logical effort of b =Logical effort of c =Logical effort of d =Logical effort of e =55. (30 points)Calculate the delays of the path G1-G2-G3-G4-G5 in the 2-input Exclusive-ORcircuit (with input buffers) below using logical effort. Also give the sizes of the Pand N transistors to achieve this delay. You may assume that the off-path capac-itance is the same as the on-path capacitance for each branch. Input capacitanceof inverter G1 = 3 units, and load capacitance driven by Gate G6 = 25 units.xyZG3G4G8G5G1G2G6G7Delay of path G1-G2-G3-G4-G5 =Sizing of G5 = P: N: Sizing of G4 = P: N:Sizing of G3 = P: N: Sizing of G2 = P: N:Sizing of G = P: 2 N: 1The assumption that off-path capacitance is the same as the on-path capacitancefor each branch is probably true for the branch at the output of G3 (assuming thesymmetric path is sized similarly), but probably not correct for the branch at theoutput of G2 (or G7, if that path is being sized). Suggest some way of improvingthe result


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UT EE 382M - EE 382M Exam 1

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