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UT EE 382M - EE 382M Syllabus

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EE 382M.7 — VLSI-1 (16860) Fall 2006Adnan Aziz ACE 6.120Office Hours: TuTh 10:00-11:00 Lecture: TuTh 11:00-12:30, ENS 302Description:We aim to study the process of implementing a digital system as a CMOS integrated circuit.The course will begin with a review of the basics of CMOS transistor operation and themanufacturing process for CMOS VLSI chips.We will then study in detail the problem of implementing logic gates in CMOS. Spec ifically,we will cover layout, design rules, and circuit families.Afterwards, we will examine techniques for timing and power analysis and clocking. Wewill also examine ways to optimize timing and power. This will be followe d by an overviewof datapath design, specifically adders and multipliers. We will also study memory arrays,including SRAM and DRAM cell and clock design.The course will conclude with a survey level treatment of various peripheral topics, includingfunctional verification, test, design-for-test, electrical effects, and future trends.We will also have guest lecturers talk about real-world design practice.Prerequisites:This course is intended for ECE graduate students. A know ledge of Electical Circuits (EE411or equivalent), and Digital Logic Design (EE316 or its equivalent) is required.Recommended text:• CMOS VLSI Design: A Circuits and Systems Perspective. N. Weste and D. Harris. 3rdEdition, 2005. Addison-Wesley.Web site: All material related to the course is available at www.ece.utexas.edu/~adnanFormat/Evaluation:I will assign approximately 6 written homeworks, which will consist of questions from thebook, and will be worth 10% of your grade. There will be two in-class midterms worth 30%,and a final project, worth 25% of your grade. Three major design projects will make up theremaining 35% of your grade.Lab due dates• Lab 1 (Layout, simulation)—due 11:59pm, Wednesday 9.20.2006• Lab 2 (Schematic design)—due 11:59pm, Wednesday 10.11.2006• Lab 3 (Verification, synthesis)—due 11:59pm, Wednesday 11.1.2006Tentative OutlineWeek MaterialPreliminariesAug 31 Introduction, historySep 5 MOS transistorsSep 7 MOS transistorsSep 12 CMOS processingCMOS circuit and logic designSep 14 Basic logic gate designSep 19 Basic physical designSep 21 Logical effortSep 26 InterconnectSep 28 Circuit familiesOct 3 AddersOct 5 Sequential elementsOct 10 ClockingOct 12 SRAMSDatapath and memoriesOct 17 Midterm 1Oct 19 ROMs, CAMs, PLAsOct 24 Datapath-1Oct 26 Datapath-2TopicsOct 31 Test-1Nov 2 Test-2Nov 7 DSM effectsNov 9 VerificationNov 14 Verification Circuit pitfallsNov 16 Low powerNov 21 Midterm 2Nov 23 THANKSGIVIINGNov 28 Clock trees, PLLsNov 30 I/ODec 5 Scaling-1Dec 7 Scaling-2Note: All departmental, college and university regulations concerning dropswill be followed. The University of Texas at Austin provides upon re quest ap-propriate academic adjustments for qualified students with disabilities. For moreinformation, contact the Office of the Dean of Students at 471- 6259,


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