EE-382M VLSI-II Static & Statistical Timing Analysis AcknowledgementsBasics of Static Timing Analysis (STA)Basics of Static Timing Analysis (STA)Basics of Static Timing Analysis (STA)Timing Analysis TechniquesStatic Timing: What Is It?Timing Analysis Basics & Key ElementsVariable Aware Timing AnalysisA Good Statistical Timer Provides:How Static Timers WorkHow Static Timers WorkHow Static Timers Work (cont.)A Note about AssumptionsStatic Timing PathsThe Timing GraphThe Timing Graph (cont.)Example Timing GraphLate Mode AnalysisLate Mode AnalysisEarly Mode AnalysisEarly Mode AnalysisStatic Timing: What’s It All About?Static Timing Analysis ExampleStatic Timing Analysis ExampleStatic Timing Analysis ExampleSTA vs. SSTAStatistical STAPre-Clock-Discussion SummaryClock ConsiderationsClocks: Those Special SignalsFootnote on Arrival Time Propagation of Clocks at Combinatorial Elements [Warning: Combining Clock Signals]Clock Phases in STAClock Phase PropagationExample: Clock Phase PropagationClocks, ATs, RATs, and SlacksLate Mode Slack CalculationLate Mode AnalysisCycle Adjustments for Tests Early Mode Slack CalculationEarly Mode AnalysisSummary of Clock ConsiderationsHow Static Timers WorkReportingTiming ModelsTiming Models (cont.)Timing Models (cont.)Timing Models (cont.)Special ConsiderationsWhat Can Happen with AT PropagationSimultaneously Switching InputsParallel DriversWire Delay ConsiderationParasitic ConsiderationsSpecial Path ControlSkew ReductionMore Call for Statistical Static Timing AnalysisSSTACorner Simulation PessimismSlack Distribution and Parametric YieldParametric yield curveCanonical variational delay modelSensitivity AnalysisSensitivity AnalysisSensitivity AnalysisSSTA SummaryEXTRASSlacks with Clock ExampleSlacks with Clock ExampleSlide Number 70Slide Number 71Importance of Establishing Required Element Setup and HoldPath ConsiderationsPath Considerations (cont.)Path Considerations (cont.)Path Considerations (cont.)Path Considerations (cont.)GlossaryGlossary (cont.)Glossary (cont.)Glossary (cont.)The University of Texas at AustinEE 382M Class Notes Foil # 1EE-382MVLSI-IIStatic & StatisticalTiming AnalysisMatthew J. Amatangelo, Intel Corp.The University of Texas at AustinEE 382M Class Notes Foil # 2AcknowledgementsJohn M. Keaty Yaping ZhanThe University of Texas at AustinEE 382M Class Notes Foil # 3Basics of Static Timing Analysis (STA)• Key points of STA– Determines worst case arrival time of signals at all pins of design elements– Does not test functionality• Does not distinguish between functional and non-functional paths– Reduce complexity of analysis to increase volume of coverage• Accuracy reduced, not compromised via use of guardbands– Underlying assumptions enable STA to produce results• Reduced accuracy, ignored connections and effects must be managed• Beware of implied synchronicity of cross domain paths– Uses ATs and RATs to determine path timing violations• Path comprised of launching and capturing components• Clocks and sequential elements define RATs• Any combinatorial element with clock input is sequential• Sorted by capturing clock. Clock phase is important.– Uses timing graph of delay arcs and checks to represent the design• Particular information is stored at each node• Long and short path analysis is performed between source and sink points of graph after ATs and RATs have been propagated through graph– Accuracy is only as good as cell timing models– Sanity check required – expected results versus actual onesThe University of Texas at AustinEE 382M Class Notes Foil # 4Basics of Static Timing Analysis (STA)• Key points of Statistical STA– Classical STA must improve by quantifying process variation as an affect on gate and wire delays– Classical STA guardbanding becomes too great vs cycle time to meet setup and hold as variations become proportionately large– SSTA provides the probability that each path passes over the range of independent variables– SSTA points to process parameters that need tweaked: • Given the circuit, find sensitivities of process parameter variance versus path delays– Components of variance must be carefully considered – PCA– Correlation is key in reducing over-pessimism– SSTA relies on a great deal of process and circuit analysis• Most fabs don’t go beyond standard STA cell libraries per corner • EDA industry generally doesn’t have access to detailed process correlation dataThe University of Texas at AustinEE 382M Class Notes Foil # 5Basics of Static Timing Analysis (STA)• Outline– Dynamic versus Static Timing– Characteristics of Static Timing– Trends: Variable Aware Static Timing Analysis– How Static Timing Analyzers Work– SSTAThe University of Texas at AustinEE 382M Class Notes Foil # 6Timing Analysis Techniques• Spice for entire networks and/or macro cross-sections.• Dynamic Simulation– Coverage dependent on quality of the set of input vectors.• circuit delays are state dependent.– Examination of logic failures not comprehensive in analyzing problems• root cause difficult to determine– Determines whether an event will occur.– Advantage - Does not time non-functional paths.– Disadvantage - How do you know all functional paths were timed?• Static Timing Analysis– Input vector pattern independent• traverses all paths between endpoints– Every source of data launch is checked at destinations or sinks• min and max delay values saved for each arc– Determines the worst possible time an event will occur– Advantage - Comprehensive, guarantees all paths are analyzed.– Disadvantage - Does not distinguish between functional & non-functional paths.The University of Texas at AustinEE 382M Class Notes Foil # 7Static Timing: What Is It?Static TimingAnalyzerInputs:NetlistConstraintsTiming ModelsParasiticsUser commandsProducts:Readable Slack Reports/HistogramsDesign Data:flat netlist, net delay file,timing model,reduced parasiticConstraints:arrival times,required arrival timesThe University of Texas at AustinEE 382M Class Notes Foil # 8Timing Analysis Basics & Key Elements• What is static timing analysis?– What it is not:• Magic -> Test your results against expectations!• It does not perform a delay based functional simulation.• It does not consider the logical functioning of the circuits (except inversions).• It does not analyze individual paths.• It doesn’t search or analyze all possible paths (Path