Circuits Design for Low PowerAgendaA quick look at the power consumption of a modern Laptop (IBM R40)A quick look at the power consumption of a ServerDesigning within limits: power & energyAgendaCMOS circuit power consumption componentsReview of Constant Field ScalingSlide 9CMOS Circuit Delay and FrequencyGate Delay TrendsMicroprocessor FrequencyDynamic EnergySupply Voltage TrendActive Power TrendRecent (180nm – 65nm) “Real Scaling”Future (65nm – 22nm) “Projected Scaling”Active-Power Reduction TechniquesCapacitance minimizationSlide 20Functional Clock GatingGlitch suppressionVoltage minimizationVoltage Scaling Reduces Active PowerDynamic Voltage-Scaling (e.g. XScale, PPC405LP)Frequency minimizationVoltage-Frequency-Scaling Measurements PowerPC 405LPShoot-through minimizationEstimating Active Power ConsumptionSlide 30Static PowerSubthreshold LeakageSlide 33Gate LeakageFuture Leakage, Standby Power TrendsStandby-Power Reduction TechniquesSlide 37Voltage Scaling Standby ReductionSupply/Power GatingMTCMOSVt / Tox selectionDevice StackingVt or/and Vdd selectionVt or/and Vdd selection (cont’d)Hitachi-SH4 leakage reductionNwell/Virtual Gnd Leakage ReductionEstimating Leakage Power ConsumptionSlide 48Low Power Circuits SummaryReferencesSlide 51Slide 52Slide 53The University of Texas at AustinEE382M VLSI-II Class NotesFoil # 1 Circuits Design for Low PowerKevin Nowka, IBM Austin Research LaboratoryEE-382MVLSI–IIThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 2 AgendaOverview of VLSI powerTechnology, Scaling, and PowerReview of scalingA look at the real trends and projections for the futureActive power – components, trends, managing, estimatingStatic power – components, trends, managing, estimatingSummaryThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 3 A quick look at the power consumption of a modern Laptop (IBM R40)Src: Mahesri et al., U of Illinois, 2004Power is all about the (digital) VLSI circuits…..and the backlight!The University of Texas at AustinEE382M VLSI-II Class NotesFoil # 4 A quick look at the power consumption of a Server Source Bose, Hot Chips 2005, cpupwr memi/o Again, it’s a VLSI problem – but this time with analog!The University of Texas at AustinEE382M VLSI-II Class NotesFoil # 5 Designing within limits: power & energy•Thermal limits (for most parts self-heating is a substantial thermal issue)-package cost (4-5W limit for cheap plastic package, 50-100W/sq-cm air cooled limit, 5k-7.5kW 19” rack)-Device reliability (junction temp > 125C quickly reduces reliability)-Performance (25C -> 105C loss of 30% of performance)-Distribution limits-Substantial portion of wiring resource, area for power dist.-Higher current => lower R, greater dI/dt => more wire, decap-Package capable of low impedance distribution-Energy capacity limits-AA battery ~1000mA.hr => limits power, function, or lifetime-Energy cost -Energy for IT equipment large fraction of total cost of ownershipThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 6 AgendaOverview of VLSI powerTechnology, Scaling, and PowerReview of scalingA look at the real trends and projections for the futureActive power – components, trends, managing, estimatingStatic power – components, trends, managing, estimatingSummaryThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 7 CMOS circuit power consumption componentsP = ½ CswVdd V f + IstVdd + IstaticVdd•Dynamic power consumption ( ½ CswVdd V f + IstVdd)–Load switching (including parasitic & interconnect)–Glitching–Shoot through power (IstVdd)•Static power consumption (IstaticVdd)–Current sources – bias currents–Current dependent logic -- NMOS, pseudo-NMOS, CML–Junction currents–Subthreshold MOS currents–Gate tunnelingThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 8 Review of Constant Field ScalingParameter Value Scaled ValueDimensions L, W, ToxL, W, ToxDopant concentrationsNa, NdNa/, Nd/Voltage VVField Capacitance CCCurrent IIPropagation time (~CV/I)ttPower (VI) P2PDensity dd/2Power density P/A P/AThese aredistributions…how do the sscale?n+STISTIpn+TransistorIsolationn+STISTIpn+TransistorSourceTransistorGateTransistorDrainConventional Silicon SubstrateElectron FlowElectron FlowAll Features Reduce in Width and ThicknessShorter Distance for Electron Flow Produce Faster TransistorsScale factor <1The University of Texas at AustinEE382M VLSI-II Class NotesFoil # 9 AgendaOverview of VLSI powerTechnology, Scaling, and PowerReview of scalingA look at the real trends and projections for the futureActive power – components, trends, managing, estimatingStatic power – components, trends, managing, estimatingSummaryThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 10 CMOS Circuit Delay and FrequencyTd = kCV/I = kCV/(Vdd-Vt)VLSI system frequency determined by:Sum of propagation delays across gates in “critical path” --Each gate delay, includes time to charge/dischargeload thru one or more FETs and interconnect delayto distribute the signal to next gate input.Sakuri -power law model of delayP = ½ CswVdd V f + IstVdd + IstaticVddThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 11 Gate Delay TrendsTd = kCV/I = kCV/(Vdd-Vt)Each technology generation, gate delay reduced about 30%(src: ITRS ’05)Consistent withC.F. ScalingP = ½ CswVdd V f + IstVdd + IstaticVddThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 12 Microprocessor FrequencyIn practice the trend is:Frequency increasing by 2X (delay decreasing by 50%), not the 1.4X (30%) for constant field scaling for 1um to 65nm node (src: ITRS ’01).Why? decreasing logic/stage and increased pipeline depth.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1technology0102030405060708090Fo4/cy cle05101520253035period (ns)cycle in FO4PeriodIntel 32b (after Hrishikesh, et. al)* Below 65nmnode return to1.4X/generation[ITRS’05] Why?P = ½ CswVdd V f + IstVdd + IstaticVddThe University of Texas at AustinEE382M VLSI-II Class NotesFoil # 13 Dynamic EnergyVddVoutddLoutddLVddoutddtddVddVCdVVCEdtdtdVCVdtVtiELVdd0200)(Vout VddVoutddLoutoutLouttoutLoutCLVCdVVCEcdtVdtdVCdtVtiEc020 021)(Energy dissipated for either output transition consumes:½ CL Vdd2CLiVddGate level energy consumption should improve as3 under constant field
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