40 60 80 100 120406080mm20. Manufacturing TestJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M.7 – VLSI IFall 2011November 7, 2011ECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 1 / 4740 60 80 100 120406080mmDealing with FaultsDesign faults: simulation and emulation, formal techniquesManufacturing faults, field failures: testing, design fortestabilityOperational faults: concurrent error detection and faulttoleranceECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 1 / 4740 60 80 100 120406080mmSilicon DebugTest the first chips back from fabricationIf you are lucky, they work the first timeIf not . . .Logic bugs vs. electrical failuresMost chip failures are logic bugs from inadequate simulationor verificationSome are electrical failuresCrosstalkDynamic nodes: leakage, charge sharingRatio failuresA few are tool or methodology failures (e.g. DRC)Fix the bugs and fabricate a corrected chipSilicon debug (or “bringup”) is primarily aNon-Recurring Engineering (NRE) cost (like design)Contrast this with manufacturing test which has to beapplied to every part shippedECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 2 / 4740 60 80 100 120406080mmPost-Silicon Validation and Manufacturing TestECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 3 / 4740 60 80 100 120406080mmSilicon Debug is a Growing Barrier to Market EntrySource: DAFCAECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 4 / 4740 60 80 100 120406080mmValidation DomainsBugs decline in number over development cycle, but cost to fixthem increasesSource: N. Hakim, IntelECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 5 / 4740 60 80 100 120406080mmWhere Bugs are FoundFunctional bugs (also known as “logic bugs”)Exist in all manufactured parts (Metric: DPM (defects permillion), fatal logic bugs result in 1M DPM)98% found before tape out, 2% post-siliconCircuit bugsNot all parts exhibit failures (< 1M DPM)Variable with Voltage, Temperature, Frequency, process andcomponent ageComputation limits to simulation (not real time) limits extentof variation combinations which can be simulated90% found pre-silicon, 10% post-siliconSource: N. Hakim, IntelECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 6 / 4740 60 80 100 120406080mmValidating a DesignDifficultiesLack of visibility to internal blocks and interconnect busesHigh latency between an internal error caused by a fault andits observation at the pinsSolutionsSoftware-Based – software monitor routines andprocessor-specific hardware allow some visibilityTest Feature-Based – reuse design-for-test (DFT) structuresfor functional debugIn-Circuit Emulation – a special “bond-out” version of thedevice is created that mirrors key internal signals on externaldevice pinsOn-chip Emulation – dedicated debug logic runs in parallel tothe normal device logicECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 7 / 4740 60 80 100 120406080mmPost-Silicon Focus AreasComplementary to pre-siliconExploit post-silicon benefitsMany cycles availablePlatform-level interactionsInstruction set architecture (ISA) and featuresMemory subsystem/hierarchyPlatform power state transitionsI/O concurrencyI/O margin characterizationCore circuit bug huntingSource: N. Hakim, IntelECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 8 / 4740 60 80 100 120406080mmShmoo PlotsHow to diagnosefailures?Difficult to accesschipsPicoprobesElectronbeamLaser voltageprobingBuilt-inself-testShmoo plotsVary voltage,frequencyLook for cause ofelectrical failuresECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 9 / 4740 60 80 100 120406080mmPlatform Validation InfrastructureSource: N. Hakim, IntelECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 10 / 4740 60 80 100 120406080mmClasses of TestsFunctional bugs in micro-architectureWeighted random instructionsArchitectural simulation patternsRandom power state transitionsDirected tests for corner casesMulti-core/multi-processor testsTests of virtualization systemMemory subsystemMemory channel activationTests for multiple cores/processorsDirected tests for memory paging, cache coherenceECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 11 / 4740 60 80 100 120406080mmCircuit BugsAffect DPM – not all die behave the same wayTiming convergence bugsSpeed path: circuit operates too slowMin-delay: circuit operating too fast (hold times)Race: circuit fails due to timing of multiple converging signalsAnalog bugsPrimarily occur in I/O buffers, PLLs, and thermal sensorsSilicon does not operate in accordance with predicted(simulated) circuit behaviorFundamentals for circuit bug huntingNeed sufficiently large population of devicesNeed to vary environmental conditionsNeed to stimulate stressful system behaviorStimulus is generally functional – failures look just likefunctional failuresECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 12 / 4740 60 80 100 120406080mmCircuit Bug Root CausesOn-die signal integrityCross-coupling induced noiseDroop-event induced noisePower delivery integrityHigh dynamic current eventsClock gating often results in high dynamic currentClock domain crossingMay cause synchronization and timing issuesProcess, Voltage, TemperaturePower state transistorsSilicon process variationSource: N. Hakim, IntelECE Department, University of Texas at Austin Lecture 20. Manufacturing Test J. A. Abraham, November 7, 2011 13 / 4740 60 80 100 120406080mmManufacturing TestA speck of dust on a wafer is sufficient to kill chipYield of any chip is < 100%Must test chips after manufacturing before delivery tocustomers to only ship good partsManufacturing testers arevery expensiveMinimize time ontesterCareful selection oftest vectorsECE Department, University of Texas at Austin Lecture 20.