Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 140 60 80 100 120406080mm13. MemoriesJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M-ICS – VLSI ISpring 2012February 25, 2012ECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 1 / 3640 60 80 100 120406080mmTaxonomy for Memory ArraysECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 1 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 240 60 80 100 120406080mmArray Architecture2nwords of 2mbits eachIf n >> m, fold by 2k into fewer rows of more columnsGood regularity easy to designVery high density if good cells are usedECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 2 / 3640 60 80 100 120406080mm12-Transistor SRAM CellBasic building block: SRAM CellHolds one bit of information, like a latchMust be read and written12-transistor (12T) SRAM cellUse a simple latch connected to bitline46 × 75 λ unit cellECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 3 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 340 60 80 100 120406080mm6-Transistor SRAM CellCell size accounts for most of array sizeReduce cell size at expense of complexity6T SRAM CellUsed in most commercial chipsData stored in cross-coupled invertersRead:Precharge bit, bit bRaise wordlineWriteDrive data onto bit,bit bRaise wordlineECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 4 / 3640 60 80 100 120406080mmSRAM ReadPrecharge both bitlines highThen turn on wordlineOne of two bitlines will be pulled down by the cellExample: A = 0, A b = 1Bit discharges, bit b stays highBut A bumps up slightlyRead stabilityA must not flipN1 >> N2ECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 5 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 440 60 80 100 120406080mmSRAM WriteDrive one bitline high, the other lowThen turn on wordlineBitlines overpower cell with new valueExample: A = 0, A b = 1, bit = 1, bit b = 0Force A b low, then A rises highWritabilityMust overpower feedback inverterN2 >> P1ECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 6 / 3640 60 80 100 120406080mmSRAM SizingHigh bitlines must not overpower inverters during readsBut low bitlines must write new value into cellECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 7 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 540 60 80 100 120406080mmSRAM Column ExampleRead WriteECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 8 / 3640 60 80 100 120406080mmSRAM LayoutCell size is critical: 26 × 45 λ (even smaller in industry)Tile cells sharing VDD, GND, bitline contactsECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 9 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 640 60 80 100 120406080mmDecodersn : 2ndecoder consists of 2nn-input AND gatesOne needed for each row of memoryBuild AND from NAND or NOR gatesStatic CMOS Pseudo-nMOSECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 10 / 3640 60 80 100 120406080mmDecoder LayoutDecoders must be pitch-matched to SRAM cellRequires very skinny gatesECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 11 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 740 60 80 100 120406080mmLarge DecodersFor n > 4, NAND gates become slowBreak large gates into multiple smaller gatesECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 12 / 3640 60 80 100 120406080mmPre-DecodingMany of the gates areredundantFactor out common gatesinto predecoderSaves areaSame path effortECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 13 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 840 60 80 100 120406080mmColumn CircuitrySome circuitry is required for each columnBitline conditioningSense amplifiersColumn multiplexingBitline ConditioningPrecharge bitlines highbefore readsEqualize bitlines to minimizevoltage difference when usingsense amplifiersECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 14 / 3640 60 80 100 120406080mmSense AmplifiersBitlines have many cells attachedExample, 32-kbit SRAM has 256 rows x 128 cols128 cells on each bitlinetpd∝ (C/I)∆VEven with shared diffusion contacts, 64C of diffusioncapacitance (big C)Discharged slowly through small transistors (small I)Sense amplifiers are triggered on a small voltage swing(reduce ∆V )Example: Differential Pair AmplifierDifferential pairrequires no clockBut alwaysdissipates staticpowerECE Department, University of Texas at Austin Lecture 13. Memories J. A. Abraham, February 25, 2012 15 / 36Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 25, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201213. Memories 940 60 80 100 120406080mmClocked Sense AmplifierClocked sense amp saves powerRequires sense clk after enough bitline swingIsolation transistors cut off large bitline capacitanceECE Department, University of Texas at Austin Lecture 13. Memories