40 60 80 100 120406080mm12. Dynamic CMOS LogicJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M-ICS – VLSI ISpring 2012February 25, 2012ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 1 / 2340 60 80 100 120406080mmDynamic LogicDynamic gates use a clocked pMOS pullupTwo modes of operation: precharge and evaluateECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 1 / 2340 60 80 100 120406080mmThe “Foot” TransistorWhat if pulldown network is ON during precharge?Use series evaluation transistor to prevent fight betweenpMOS and nMOS transistorsECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 2 / 2340 60 80 100 120406080mmLogical EffortECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 3 / 2340 60 80 100 120406080mmMonotonicityDynamic gates require monotonicallyrising inputs during evaluation0 → 00 → 11 → 1But not 1 → 0ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 4 / 2340 60 80 100 120406080mmMonotonicity WoesBut dynamic gates produce monotonically falling outputsduring evaluationIllegal for one dynamic gate to drive another!ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 5 / 2340 60 80 100 120406080mmDomino GatesFollow dynamic stage with inverting static gateDynamic/static pair is called domino gateProduces monotonic outputsECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 6 / 2340 60 80 100 120406080mmDomino OptimizationsEach domino gate triggers next one, like a string of dominostoppling overGates evaluate sequentially, precharge in parallelEvaluation is more critical than prechargeHI-skewed static stages can perform logicECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 7 / 2340 60 80 100 120406080mmDual-Rail DominoDomino only performs noninverting functions:AND, OR but not NAND, NOR, or XORDual-rail domino solves this problemTakes true and complementary inputsProduces true and complementary outputssig h sig l Meaning0 0 Precharged0 1 ‘0’1 0 ‘1’1 1 InvalidECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 8 / 2340 60 80 100 120406080mmExample: AND/NANDGiven A h, A l, B h, B lCompute Y h = A * B, Y l = ∼(A * B)Pulldown networks are conduction complementsECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 9 / 2340 60 80 100 120406080mmExample: XOR/XNORSometimes possible to share transistorsSharing works well in implementations of symmetric functionsSee papers on “relay logic” published over 50 years agoECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 10 / 2340 60 80 100 120406080mmLeakageDynamic node floats high during evaluationTransistors are leaky (Ioff6= 0)Dynamic value will leak away over timeFormerly milliseconds, now nanoseconds!Use keeper to hold dynamic nodeMust be weak enough not to fight evaluationLeakage Power!ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 11 / 2340 60 80 100 120406080mmCharge SharingDynamic gates suffer from charge sharingVx= Vy=CyCx+ CyVDDECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 12 / 2340 60 80 100 120406080mmSecondary PrechargeSolution: add secondary precharge transistorsTypically need to precharge every other nodeBig load capacitance on Y helps as wellECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 13 / 2340 60 80 100 120406080mmNoise SensitivityDynamic gates are very sensitive to noiseInputs: VIH≈ VtnOutputs: floating output susceptible noiseNoise sourcesCapacitive crosstalkCharge sharingPower supply noiseFeedthrough noiseAnd more!Chip power supply voltage mapwhen executing a programECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 14 / 2340 60 80 100 120406080mmAlternating N & P Domino LogicECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 15 / 2340 60 80 100 120406080mmCascade Voltage Switch Logic (CVSL)ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 16 / 2340 60 80 100 120406080mmDynamic CVSL XOR GateECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 17 / 2340 60 80 100 120406080mmDual-Rail Domino Full Adder DesignVery fast, but large and power hungryUsed in very fast multipliersECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 18 / 2340 60 80 100 120406080mm“Manchester” AddersECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 19 / 2340 60 80 100 120406080mmDomino SummaryDomino logic is attractive for high-speed circuits1.5 2x faster than static CMOSMany ChallengesMonotonicityLeakageCharge sharingNoiseUsed in previous generation high-performance microprocessorsand in some recent embedded processorsECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 20 / 2340 60 80 100 120406080mmDomino Logic in Current DesignsDomino design from Intrinsity used in 1-GHz 0.75W ARMCortex A8 from Samsung (Intrinsity later acquired by Apple)Fast Domino (called “Fast14 NDL”) gates are insertedselectively into critical speed paths, with custom SRAMs andoptimized synthesized logic elsewhereStandard power saving techniques are also usedDomino gates are clocked by multiphase clocksA type of “super-pipeline” where the domino footers form thebarrier for the pipeline operation(Source: Electronic Design – Embedded, August 29, 2009)ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, February 25, 2012 21 / 2340 60 80 100 120406080mmIntrinsity OR/NOR Implementation with “N-nary