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UT EE 382M - Sequential Elements

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Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 140 60 80 100 120406080mm11. Sequential ElementsJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M-ICS – VLSI ISpring 2012February 4, 2012ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 1 / 4040 60 80 100 120406080mmFloor PlanHow do youestimate blockareas?Begin withblock diagramEach block hasInputsOutputsFunctionType: array,datapath,randomlogicEstimationdepends on typeof logicMIPS FloorplanECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 1 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 240 60 80 100 120406080mmArea EstimationArraysLayout basic cellCalculate core area from number of cellsAllow area for decoders, column circuitryDatapathsSketch slice planCount area of cells from cell libraryEnsure wiring is possibleRandom LogicCompare complexity do a design you have doneFor design in a new technology, estimate from scaling design inthe old technologyECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 2 / 4040 60 80 100 120406080mmMIPS Slice PlanECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 3 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 340 60 80 100 120406080mmTypical Layout DensitiesTypical number of high quality layout given belowDerate by 2 for class projects to allow routing and somesloppy layoutAllocate space for big wiring channelsElement AreaRandom logic (2 metal layers) 1000 – 1500 λ2/transistorDatapath 250 – 750 λ2/transistoror, 6W L + 360λ2/transistorSRAM 1000 λ2/bitDRAM 100 λ2/bitROM 100 λ2/bitECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 4 / 4040 60 80 100 120406080mmSequencingCombinational logicOutput depends on current inputsSequential logicOutput depends on current and previous inputsRequires separating previous, current, futureCalled state or tokensExample, Finite-State Machine (FSM), pipelineECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 5 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 440 60 80 100 120406080mmSequencing, Cont’dIf tokens moved through pipeline at constant speed, nosequencing elements would be necessaryExample, fiber-optic cableLight pulses (tokens) are sent down cableNext pulse sent before first reaches end of cableNo need for hardware to separate pulsesBut dispersion sets min time between pulsesThis is called wave pipelining in circuitsIn most circuits, dispersion is highDelay fast tokens so they don’t catch slow onesECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 6 / 4040 60 80 100 120406080mmSequencing OverheadUse flip-flops to delay fast tokens so they move throughexactly one stage each cycleInevitably adds some delay to the slow tokensMakes circuit slower than just the logic delayCalled sequencing overheadSome people call this clocking overheadBut it applies to asynchronous circuits tooInevitable side effect of maintaining sequenceECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 7 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 540 60 80 100 120406080mmSequencing ElementsLatch: Level sensitiveAlso called transparent latch, D latchFlip-Flop: Edge triggeredAlso called master-slave flip-flop, D flip-flop, D register, D FlopTiming DiagramsTransparentOpaqueEdge-triggerECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 8 / 4040 60 80 100 120406080mmLatch DesignsPass Transistor Latch+ Tiny+ Low clock load– Vtdrop– Non-restoring– Back driving– Output noise sensitivity– Dynamic– Diffusion inputUsed in the 1970sECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 9 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 640 60 80 100 120406080mmLatch Designs, Cont’dTransmission Gate Latch+ No Vtdrop– Requires inverted clockInverting Buffer Latch+ Restoring+ No Backdriving+ Fixes eitherOutput noise sensitivityOr diffusion input– Inverted outputECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 10 / 4040 60 80 100 120406080mmLatch Designs, Cont’dLatch with Tristate Feedback+ Static– Backdriving riskStatic latches are nowessentialLatch with Buffered Input+ Fixes diffusion input+ Non-invertingECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 11 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4, 2012Introduction to VLSI Design, VLSI I–ICS, Spring 201211. Sequential Elements 740 60 80 100 120406080mmLatch Designs, Cont’dLatch with Buffered OutputWidely used in standard cells+ No backdriving+ Very robust (most important)– Rather large– Rather slow (1.5 – 2 FO4 delays)– High clock loadingDatapath Latch+ Smaller, faster- Unbuffered inputECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 12 / 4040 60 80 100 120406080mmFlip-Flop DesignFlip-flop is built as a pair of back-to-back latchesECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, February 4, 2012 13 / 40Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, February 4,


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UT EE 382M - Sequential Elements

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