EE 382M.7 — VLSI-1 (17235) Fall 2007Adnan Aziz ACE 6.120Office Hours: TuTh 11:00-12:00 Lecture: TuTh 12:30-20-0, ENS 126Description:We aim to study the process of implementing a digital system as a CMOS integrated circuit.The course will begin with a review of the basics of CMOS transistor operation and themanufacturing process for CMOS VLSI chips.We will then study in detail the problem of implementing logic gates in CMOS. Spec ifically,we will cover layout, design rules, and circuit families.Afterwards, we will examine techniques for analysing and optimizing timing and power at thecircuit level. We will study sequential elements—latches and flops—and clocking. This willbe followed by an overview of datapath design: detection logic, shifters, comparators, adders,and multipliers. We will also study memories, specifically the workhorse 6-T SRAM cell aswell as peripheral decode logic.The course will conclude with a survey level treatment of various topics, including advancedcircuit design techniques, clock tree design, functional verification, test, design-for-test, elec-trical effects, packaging, and future trends.Prerequisites:This course is intended for ECE graduate students. A knowledge of Electical Circuits (EE411or equivalent), and Digital Logic Design (EE316 or its equivalent) is required.Recommended text:• CMOS VLSI Design: A Circuits and Systems Perspective. N. Weste and D. Harris. 3rdEdition, 2005. Addison-Wesley.Web site: All material related to the course is available at www.ece.utexas.edu/~adnanFormat/Evaluation:I will assign approximately 6 written homeworks, which will consist of questions from thebook, and will be worth 5% of your grade. There will b e two in-class midterms worth 35%,and a final project, worth 25% of your grade. Three major design projects will make up theremaining 35% of your grade.OutlineWeek MaterialPreliminariesAug 30 Introduction, historySep 4 MOS transistors, Lab 1 presentationSep 6 MOS transistorsSep 11 CMOS processingCMOS circuit and logic designSep 13 Basic logic gate designSep 18 Basic physical designSep 20 Logical effortSep 25 Interconnect, Lab 2 presentationSep 27 Circuit familiesOct 2 AddersOct 4 Sequential elementsOct 9 ClockingOct 11 SRAMSDatapath and memoriesOct 16 ROMs, CAMs, PLAsOct 18 Datapath-1, Lab 3 presentationOct 23 Midterm 1Oct 25 Datapath-2TopicsOct 30 Test-1Nov 1 Test-2Nov 6 DSM effectsNov 8 VerificationNov 13 Verification Circuit pitfallsNov 15 Low powerNov 20 Midterm 2Nov 22 THANKSGIVIINGNov 27 Clock trees, PLLsNov 29 I/ODec 4 Scaling-1Dec 6 Scaling-2Note: All departmental, college and university regulations concerning dropswill be followed. The University of Texas at Austin provides upon request ap-propriate academic adjustments for qualified students with disabilities. For moreinformation, contact the Office of the Dean of Students at 471- 6259,