40 60 80 100 120406080mm18. Design VerificationJ. A. AbrahamDepartment of Electrical and Computer EngineeringThe University of Texas at AustinEE 382M.7 – VLSI IFall 2011October 31, 2011ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 1 / 3740 60 80 100 120406080mmReliability in the Life of an Integrated Circuit – IDesignDesign “bugs”Verification (Simulation, Formal)FabricationWaferProcess variations,defectsProcess MonitorsECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 1 / 3740 60 80 100 120406080mmReliability in the Life of an Integrated Circuit – IIWafer ProbePackageTesterTest cost,coverageDesign for Test,Built-In Self TestSystemApplicationTest escapes,wearout,environmentSystem Self-Test,Error Detection,Fault ToleranceECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 2 / 3740 60 80 100 120406080mmAnalyzing Complex DesignsNeed to (implicitly) search a very large state spaceFind bugs in a design – verification processGenerate tests for faults in a manufactured chipBasic algorithms for analyzing even combinational blocks (SAT,ATPG) are NP-completeApproaches to deal with real designsExploit hierarchy in the designDevelop abstractions for parts of a designCost of a new mask set can be on the order of $1+ Million for alarge chipCannot afford mistakesWant working “first silicon”ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 3 / 3740 60 80 100 120406080mmMany Aspects of VerificationVerifying the functional correctness of the designPerformance verificationArchitecture level (number of clocks to perform a function)Timing verificationCircuit level (how fast can we clock?)Verifying power consumptionVerifying signal integrity and variation toleranceChecking correct implementation of specifications at eachlevelECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 4 / 3740 60 80 100 120406080mmThe Verification ProblemNeed to deal with this complexityA subtle bug could produce an incorrect result in a specificstate for a specific data inputSeen as a “sequence dependency” when simulating a design(specific sequence of inputs to reach the erroneous state)ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 5 / 3740 60 80 100 120406080mmThe (In)Famous Pentium FDIV ProblemGraph of x, y, x/y in a small region by Larry HoyleECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 6 / 3740 60 80 100 120406080mmState-Space ExplosionMay need to check a very large number of states to uncover a bugProblem: the number of protons in the universe is around 1080,which is less than the number of states for a system with 300storage elements!ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 7 / 3740 60 80 100 120406080mmWhat is a “Bug”?Design does not match the specificationOne problem: complete (and consistent) specifications maynot exist for many productsFor example, the difficulty in designing an X86 compatiblechip is not in implementing the X-86 instruction setarchitecture, but in matching the behavior with Intel chipsSomething which the customer will complain aboutMarketing: “It’s not a bug, it’s a feature”ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 8 / 3740 60 80 100 120406080mmDesign FlawsAbout half of the flaws are functional flawsNeed verification methods to find and fix logical and functionalflawsECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 9 / 3740 60 80 100 120406080mmDesign Bug Distribution in Pentium 4Type of Bug %“Goof” 12.7Miscommunication 11.4Microarchitecture 9.3Logic/Microcode Changes 9.3Corner Cases 8.0Power Down 5.7Documentation 4.4Complexity 3.9Initialization 3.4Incorrect RTL Assertions 2.8Design Mistake 2.6Source: EE Times, July 4, 200142 Million TransistorsHigh-level description: 1+ millionlines of RTL100 high-level bugs found throughformal verificationECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 10 / 3740 60 80 100 120406080mmDesign EffortVerification is becoming an increasing part of the design effortECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 11 / 3740 60 80 100 120406080mmVerification EffortSource: 1999 ITRSOver 50% – 80% of design effort is in verificationECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 12 / 3740 60 80 100 120406080mmDesign and Verification GapBlame it on Moore’s LawThe number of transistors on a chip is increasing every year(approx. 58%)Design productivity, facilitated by EDA tool improvements,grows only about 21% per yearThese numbers have held constant for two decadesECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 13 / 3740 60 80 100 120406080mm“Bug” Introduction and DetectionECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 14 / 3740 60 80 100 120406080mmRe-Spins because of Functional FlawsTom FitzpatrickEE Times, December 5, 2005ECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 15 / 3740 60 80 100 120406080mmDesign and Implementation VerificationECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 16 / 3740 60 80 100 120406080mmVerification ApproachesSimulation (the most popular verification method)Cycle based, functional simulation for billions of cyclesGood coverage metrics usually not availableComputationally very expensive, slightest optimization hashuge impactEmulationCapital intensiveMap design to be verified on FPGAsRun OS and application at MHz ratesFormal verificationExhaustive verification of small modulesECE Department, University of Texas at Austin Lecture 18. Design Verification J. A. Abraham, October 31, 2011 17 / 3740 60 80 100 120406080mmEvaluating the Complete DesignIs there a