Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6 002 Circuits Electronics Spring 2005 Problem Set 4 Issued 2 23 05 Due 3 2 05 Exercise 4 1 Consider the logic circuit that implements OUT IN1 IN2 IN3 Express OUT as a function of IN1 IN2 and IN3 in the form of a truth table Also implement this logic circuit using logic symbols and using a small number of n channel MOSFETs and pull up resistors Exercise 4 2 In the circuit shown below an inverter is loaded with a resistor For this circuit determine vOUT as a function of vIN Also graph and clearly label this input output relation To do so model the MOSFET as a switch having a threshold voltage of 1 V and an on state resistance of 1 k 10 k 2V 90 k vIN vOUT Problem 4 1 Following the node method develop a set of simultaneous equations for the network shown below that can be solved to determine the unknown node voltages e1 e2 and e3 Express the set of equations in the form e1 G e2 S e3 where G is a 3 3 matrix of conductance terms and S is a 3 1 vector of terms involving the independent sources You need not solve the set of equations for the node voltages Note that e4 is not included in the analysis because it is directly sourced by the dependent voltage source from ground and the source voltage can be expressed in terms of the first three node voltages In this sense it is treated like an independent voltage source Nonetheless state how e4 can be determined from e1 e2 and e3 once the latter node voltages are determined e1 e2 i R3 G e2 e1 R4 R2 e4 e3 R5 V R1 Ri I Problem 4 2 Determine the Thevenin equivalent of each network shown below Note that these networks contain dependent sources R1 R2 v R3 gu u u Au V R Problem 4 3 This problem studies the two stage n channel MOSFET amplifier shown below The two stages are built with identical MOSFETs and pull up resistors A simplified model for the MOSFET is also given below The simplification is that the triode region of operation is compressed 2 2 which becomes a common curve of operation for v onto the curve iD KvDS GS VT vDS Hint a load line analysis may help solve this problem A Determine the range of vIN over which MOSFET M1 operates in cutoff Also determine vMID for this operating range B Assuming that MOSFET M1 operates in its saturation region determine vMID as a function of vIN Also determine the range of vMID and the range of vIN that correspond to the saturated operation of MOSFET M1 C For values of vIN that are above the range found in Part B MOSFET M1 operates in its 2 2 Determine triode region which in the model below is compressed onto the curve iD KvDS vMID for vIN in this range of operation D Using the results of Parts A B and C determine vOUT as a function of vMID for the cutoff saturation and triode regions of operation of MOSFET M2 For each region state the corresponding operating range of vMID and vOUT E Assuming that both MOSFETs operate in their saturation regions determine vOUT as a function of vIN Also determine the range of vMID and then the corresponding range of vIN over which both MOSFETs operate in their saturation regions F Determine the small signal gain of the amplifier as a function of the operating point input VIN assuming that this operating point falls within the range found in Part E That is determine dvOUT dvIN evaluated at VIN G Let K 0 02 A V2 RD 1 k VS 10V and VT 1 V Plot vMID as a function of vIN for 0 vIN 3 V On the same graph plot vOUT as a function of vIN over the same range of vIN Hint this is particularly simple if you are familiar with MatLab on Athena Observe the differences of the two plots Save a copy of your solutions to help with Homework 5 VS R iD R vIN vMID vOUT Triode iD KvDS2 2 vGS VT vDS Saturation iD K vGS VT 2 2 0 vGS VT vDS vDS Cutoff iD 0 vGS VT 0 Problem 4 4 An NPN bipolar junction transistor NPN BJT is a three terminal device Its terminals are referred to as the base the collector and the emitter The symbol for the NPN BJT is shown below along with the voltage and current definitions for this BJT when it is viewed as a two port device Here the Base Emitter port acts as a control port and the Collector Emitter port acts as a power port much like the Gate Source and Drain Source ports of an n channel MOSFET respectively Figures 1 and 2 below describe the greatly idealized behavior of an NPN BJT in terms of its port variables Figure 1 describes the behavior of the control port and shows how iB is related to vBE Figure 2 describes the behavior of the power port and shows how iC is related to vCE for various values of iB In general for iB 0 and vCE 0 iC iB where is a gain constant This problem investigates the use of the NPN BJT described by Figures 1 and 2 to construct an amplifier The amplifier is shown in Figure 3 Assume that VS VD A Determine iB as a function of vIN Sketch and clearly label the result Hint a load line analysis might provide useful insight given the nonlinear behavior shown in Figure 1 B Determine vOUT as a function of iB note that vOUT vCE for the amplifier shown in Figure 3 Sketch and clearly label the result Hint a load line analysis might provide useful insight given the nonlinear behavior shown in Figure 2 C Combine the results of Parts A and B to determine vOUT as a function of vIN Sketch and clearly label the result Symbol Two Port Definitions Collector Figure 1 iC iB vCE vBE Base iB Emitter vBE VD Figure 3 iC i3 i2 i1 Figure 2 RC iB i3 iB i2 RB iB i1 iB 0 vCE VS vIN vOUT
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