GCD VLSI s Hello World Part a CS250 Laboratory 1a Version 09072011 Written by Yunsup Lee 2010 Updated by Brian Zimmer 2011 Overview For this assignment you will become familiar with the VLSI tools you will use throughout this semester learn how a design flows through the toolflow and practice Verilog coding Specifically you will write an RTL model of a greatest common divisor GCD circuit synthesize and place and route the design simulate at every stage and analyze power Deliverables This lab is due Monday September 12th at 1pm Deliverables for this lab are a build results and reports generated by VCS DC Compiler Formality IC Compiler PrimeTime PX checked into Git b written answers to the questions given at the end of this document checked into git as writeup report pdf or writeup report txt You are encouraged to discuss your design with others in the class but you must turn in your own work VLSI Toolflow Introduction Figure 1 shows the toolflow you will be using for the first lab You will use Synopsys VCS vcs to simulate and debug your RTL design After you get your design right you will use Synopsys Design Compiler dc shell xg t to synthesize the design Synthesis is the process of transforming an RTL model into a gate level netlist You will use Synopsys Formality fm shell to formally verify that the RTL model and the gate level model match VCS is used again to simulate the synthesized gate level netlist After obtaining a working gate level netlist you will use Synopsys IC Compiler icc shell to place and route the design Placement is the process by which each standard cell is positioned on the chip while routing involves wiring the cells together using various metal layers The tools will provide feedback on the performance and area of your design after both synthesis and place and route The results from place and route are more realistic but require much more time to generate After place and route you will generate and simulate the final gate level netlist using VCS Finally you will use this gate level simulation as a final test for correctness and to generate transition counts for every net in the design Synopsys PrimeTime PX pt shell takes these transition counts as input and correlate them with the capacitance values in the final layout to produce estimated power measurements The diagram below shows how every tools works together CS250 Lab Assignment 1a Version 09072011 Fall 2011 Verilog Source Behav Verilog Source RTL VCS VCS Behav Sim RTL Sim Execute SIM Execute SIM 2 Std Cell Library Constraints Design Compiler Gate Level Netlist Guidance File Delay File Constraints Timing File Area Formality VPD Test Outputs DVE GUI VPD Test Outputs IC Compiler DP TLU Files Verification Results Floor Plan Design Vision GUI DVE GUI IC Compiler P R VCS Post Syn Sim Gate Level Netlist Delay File Constraints Timing File Area Layout Parasitics File Execute SIM VCS VPD Test Outputs IC Compiler GUI Post P R Sim DVE GUI Execute SIM VPD DVE GUI Test Outputs VPD2VCD VCD PrimeTime Power Estimates Figure 1 CS250 Toolflow for Lab 1 CS250 Lab Assignment 1a Version 09072011 Fall 2011 3 Prerequisites As you can easy tell from the diagram many different tools are needed to take even a simple design from RTL all the way to transistor level implementation Each tool is immensely complicated and many engineers in industry specialize in only one In order to produce a VLSI design in a single semester we will need to understand a little about every one Each tool has a GUI interface However most inputs that the tools need are the same for every design iteration and become repetitive to type so tcl scripts provide all of the inputs needed When you use the GUI in the terminal window you will see the textual equivalent of each click and these commands can be added to scripts To keep files organized each piece of the toolflow has its own build directory and its own Makefile The Makefile initializes the program and points at the setup scripts A top level Makefile runs each program in succession so that ideally a single command will push an RTL design all of the way through the flow without any repetitive intervention This will also allow for easy design space exploration eg tweak a variable and see how energy area and performance change Tutorials have been written to provide more in depth information than this lab It is highly recommended that you skim these tutorials before beginning the lab revisit the tutorials in more depth after you have completed that lab and revist them again later in the quarter once the process begins to make more sense These tutorials work best as companions to the labs Tutorial Tutorial Tutorial Tutorial Tutorial Tutorial 1 2 4 5 6 7 Using Git to Manage Source RTL Bits and Pieces of CS250 s Toolflow Simulating Verilog RTL using Synopsys VCS RTL to Gates Synthesis using Synopsys Design Compiler Automatic Placement and Routing using Synopsys IC Compiler Power Analysis using Synopsys PrimeTime PX CS250 Lab Assignment 1a Version 09072011 Fall 2011 4 Getting Started You can follow along through the lab yourself by typing in the commands marked with a symbol at the shell prompt To cut and paste commands from this lab into your bash shell and make sure bash ignores the character just use an alias to undefine the character like this alias Note OS X Preview will not copy newlines correctly so use Adobe Reader All of the CS250 laboratory assignments should be completed on an EECS Instructional machine Please see the course website and follow all of the instructions for setting up your computing resources Remember you will need to source a setup script in order for these instructions to work This bash script contains the location of each tool s binary and also sets up important environment variables Make sure you have followed class setup instructions before starting these are posted on the website You will be using Git to manage your CS250 laboratory assignments Please see Tutorial 1 Using Git to Manage Source RTL for more information on how to use Git Every student has their own directory in the repository which is not accessible to other students The remote repository is hosted on github com In order for these instructions to work you must have told your GSI what your github com username is We have a template repository which contains all of the files that we provide for your lab You will clone this template repository then change your remote repository to be your private repository Therefore you