Chisel Tutorial Jonathan Bachrach Krste Asanovic John Wawrzynek EECS Department UC Berkeley jrb krste johnw eecs berkeley edu November 19 2011 1 Introduction This document is a tutorial introduction to Chisel Constructing Hardware In a Scala Embedded Language Chisel is a hardware construction language embedded in the high level programming language Scala At some point we will provide a proper reference manual in addition to more tutorial examples In the meantime this document along with a lot of trial and error should set you on your way to using Chisel Chisel is really only a set of special class definitions predefined objects and usage conventions within Scala so when you write a Chisel program you are actually writing a Scala program However for the tutorial we don t presume that you understand how to program in Scala We will point out necessary Scala features through the Chisel examples we give and significant hardware designs can be completed using only the material contained herein But as you gain experience and want to make your code simpler or more reusable you will find it important to leverage the underlying power of the Scala language We recommend you consult one of the excellent Scala books to become more expert in Scala programming Chisel is still in its infancy and you are likely to encounter some implementation bugs and perhaps even a few conceptual design problems However we are actively fixing and improving the language and are open to bug reports and suggestions Even in its early state we hope Chisel will help designers be more productive in building designs that are easy to reuse and maintain Through the tutorial we format commentary on our design choices as in this paragraph You should be able to skip the commentary sections and still fully understand how to use Chisel but we hope you ll find them interesting We were motivated to develop a new hardware language by years of struggle with existing hardware description languages in our research projects and hardware design courses Verilog and VHDL were developed as hardware simulation languages and only later did they become a basis for hardware synthesis Much of the semantics of these languages are not appropriate for hardware synthesis and in fact many constructs are simply not synthesizable Other constructs are non intuitive in how they map to hardware implementations or their use can accidently lead to highly inefficient hardware structures While it is possible to use a subset of these languages and yield acceptable results they nonetheless present a cluttered and confusing specification model particularly in an instructional setting However our strongest motivation for developing a new hardware language is our desire to change the way that electronic system design takes place We believe that it is important to not only teach students how to design circuits but also to teach them how to design circuit generators programs that automatically generate designs from a high level set of design parameters and constraints Through circuit generators we hope to leverage the hard work of design experts and raise the level of design abstraction for everyone To express flexible and scalable circuit construction circuit generators must employ sophisticated programming techniques to make decisions concering how to best customize their output circuits according to high level parameter values and constraints While Verilog and VHDL include some primitive constructs for programmatic circuit generation they lack the powerful facilities present in modern programming languages such as object oriented programming type inference support for functional programming and reflection Instead of building a new hardware design language from scratch we chose to embed hardware construction primitives within an existing language We picked Scala not only because it includes the programming features we feel are important for building circuit generators but because it was specifically developed as a base for domain specific languages 1 2 Hardware expressible in Chisel The initial version of Chisel only supports the expression of synchronous RTL Register Transfer Level designs with a single common clock Synchronous RTL circuits can be expressed as a hierarchical composition of modules containing combinational logic and clocked state elements Although Chisel assumes a single global clock local clock gating logic is automatically generated for every state element in the design to save power Modern hardware designs often include multiple islands of logic where each island uses a different clock and where islands must correctly communicate across clock island boundaries Although clock crossing synchronization circuits are notoriously difficult to design there are known good solutions for most scenarios which can be packaged as library elements for use by designers As a result most effort in new designs is spent in developing and verifying the functionality within each synchronous island rather than on passing values between islands In its current form Chisel can be used to describe each of the synchronous islands individually Existing tool frameworks can tie together these islands into a complete design For example a separate outer simulation framework can be used to model the assembly of islands running together It should be noted that exhaustive dynamic verification of asynchronous communications is usually impossible and that more formal static approaches are usually necessary This version of Chisel also only supports binary logic and does not support tri state signals We focus on binary logic designs as they constitute the vast majority of designs in practice We omit support for tri state logic in the current Chisel language as this is in any case poorly supported by industry flows and difficult to use reliably outside of controlled hard macros 3 Datatypes in Chisel Chisel datatypes are used to specify the type of values held in state elements or flowing on wires While hardware designs ultimately operate on vectors of binary digits other more abstract representations for values allow clearer specifications and help the tools generate more optimal circuits In Chisel a raw collection of bits is represented by the Bits type Signed and unsigned integers are considered subsets of fixed point numbers and are represented by types Fix and UFix respectively Signed fixed point numbers including integers are represented using two s complement format