EEC 116 Lecture #11: Implementation StrategiesAnnouncementsOutlineAbstraction of Design ComplexityDesign Abstraction LevelsAbstraction of Design ComplexityHierarchical AbstractionWhy Learn About Circuits and Layout Then?Design Aspects that “Defy Hierarchy”Full CustomFull Custom Design ExampleStandard CellStandard CellStandard Cell — ExampleCombination Standard Cell and Full Custom“Soft” MacroModulesGate ArrayUnprogrammed Gate ArrayProgrammed Gate ArrayGate Array — Sea-of-GatesUnprogrammed Sea-of-Gates ArrayProgrammed Sea-of-Gates ArrayGate ArrayField Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)Heterogeneous Programmable PlatformsDesign at a Crossroad: System-on-a-ChipA SoC Example: High Definition TV ChipAsynchronous Array of Simple ProcessorsDiagram of a 3x3 AsAPSimple Diagram of Front-End Design FlowSimple Diagram of Back-End Design FlowBack-end Design of AsAPFlow of Placement and RoutingImport Needed FilesFloorplanPlacement and In-Placement OptimizationClock TreeRoutingVerification After LayoutUseful Design and Simulation ToolsUseful Verification ToolsNext Topics: Low Power and DFMEEC 116 Lecture #11:Implementation StrategiesRajeevan Amirtharajah Bevan BaasZhiyi YuUniversity of California, DavisAmirtharajah, EEC 116 Fall 2011 2Announcements• Lab 5 due Wednesday, Nov. 23• Homework 5 due Monday, Nov. 28• Lab 6 due Friday, Dec. 2Amirtharajah, EEC 116 Fall 2011 3Outline• Review and Finish: Memories• Implementation Strategies: Rabaey Ch. 1, 8 (Kang & Leblebici, Ch. 1)Amirtharajah, EEC 116 Fall 2011 4Abstraction of Design Complexity• Design complexity– Typically tens of transistors in analog circuits• Each is normally hand crafted along with placement and wiring– Hundreds of transistors• Each can be hand crafted– Thousands to 100s of thousands of transistors• Must find regularity in structure and exploit it (re-use cells)• Ex: memory– Millions to billions of transistors• Must find high-level regularity in structure and exploit it (re-use modules and subsystems)• Ex: System on Chip (SOC)Amirtharajah, EEC 116 Fall 2011 5Design Abstraction Levelsn+n+SGD+DEVICECIRCUITGATEMODULESYSTEMFUNCTIONAL UNIT, orAmirtharajah, EEC 116 Fall 2011 6Abstraction of Design Complexity• Levels–Device–Circuit–Gate– Module or functional unit (e.g., adder, memory, etc.)– Sub-system (e.g., processor, display driver, network interface, etc.)• Methods to abstract complexity– Sophisticated Computer-Aided-Design (CAD) tools– Standard cell librariesAmirtharajah, EEC 116 Fall 2011 7Hierarchical Abstraction• Example: While designing at the gate level, we do not consider what is inside each gateANDANDANDORORCarry-OutACABBCAmirtharajah, EEC 116 Fall 2011 8Why Learn About Circuits and Layout Then?• Best designers can:– Build model abstractions– Understand limitations of models• Wire or interconnect performance• Changes with technology scaling• Abstractions limit maximum attainable performance and energy-efficiency– Multi-disciplinary view needed• Troubleshooting and debuggingAmirtharajah, EEC 116 Fall 2011 9Design Aspects that “Defy Hierarchy”• Clock distribution– Timing skew• Power distribution– Sufficient current handling– Adequate noise suppressionAmirtharajah, EEC 116 Fall 2011 10Full Custom• All transistors and interconnect drawn by hand• Full control over sizing and layout• Highest area density and higher performance• Longest time to design “maturity”[figure from S. Hauck]Amirtharajah, EEC 116 Fall 2011 11Full Custom Design Example• Multiplier ChipAmirtharajah, EEC 116 Fall 2011 12Standard Cell• Constant-height cells• Regular “pin”locations• Cells represent gates, latches, flip-flops• Placed and routed by software[figure from S. Hauck]Amirtharajah, EEC 116 Fall 2011 13Standard Cell• Channels for routing only in older technologies (not necessary with modern processes with many levels of interconnect)[figure from S. Hauck]Amirtharajah, EEC 116 Fall 2011 14Standard Cell — Example[Brodersen92]• Application-Specific Integrated Circuit (ASIC)• Hardwired combination of standard cells implements a fixed logic function or FSM (e.g., video codec)Amirtharajah, EEC 116 Fall 2011 15Combination Standard Cell and Full Custom[figure from S. Hauck]Amirtharajah, EEC 116 Fall 2011 16“Soft” MacroModulesSynopsys DesignCompilerSource: Digital Integrated Circuits, 2nd ©Amirtharajah, EEC 116 Fall 2011 17Gate Array• Polysilicon and diffusion are the same for all designs• Metal layers customized for particular chipsn‐typediffusionpolysiliconp‐typediffusionPMOStransistorNMOStransistorAmirtharajah, EEC 116 Fall 2011 18Unprogrammed Gate ArrayIsolation Provided by SpacingAmirtharajah, EEC 116 Fall 2011 19Programmed Gate Array• Metal connections made to create particular function• What logic gate is this?Amirtharajah, EEC 116 Fall 2011 20Gate Array — Sea-of-Gatesrows ofcellsrouting channeluncommittedVDDGNDpolysiliconmetalpossiblecontactIn1 In2 In3 In4OutUncommited CellCommitted Cell (4-input NOR)Source: Digital Integrated Circuits, 2nd ©Amirtharajah, EEC 116 Fall 2011 21Unprogrammed Sea-of-Gates ArrayAmirtharajah, EEC 116 Fall 2011 22Programmed Sea-of-Gates ArrayIsolation Provided by Cutoff BiasAmirtharajah, EEC 116 Fall 2011 23Gate Array• Polysilicon and diffusion the same for all designs• 0.125 um example[figure from LETI]Amirtharajah, EEC 116 Fall 2011 24Field Programmable Gate Array (FPGA)• Metal layers now programmable with SRAM instead of hardwired during manufacture as with a gate array • Cells contain general programmable logic and registers[figure from S. Hauck]Amirtharajah, EEC 116 Fall 2011 25Field Programmable Gate Array (FPGA)• Chips can now be “designed” with software• User pays for up-front chip design costs– All costs: full-custom, standard cell– Half: gate array– Shared: FPGA• User writes code (e.g., Verilog), compiles it, and downloads into the chip– Can be used to prototype standard cell (ASIC) designAmirtharajah, EEC 116 Fall 2011 26Heterogeneous Programmable PlatformsXilinx Vertex-II ProCourtesy XilinxHigh-speed I/OEmbedded PowerPCEmbedded memoriesHardwired multipliersFPGA FabricAmirtharajah, EEC 116 Fall 2011 27Design at a Crossroad: System-on-a-ChipRAM500 k Gates FPGA+ 1 Gbit DRAMPreprocessingMulti-SpectralImagerμCsystem+2 GbitDRAMRecog-nitionAnalog64 SIMD ProcessorArray + SRAMImage Conditioning100 GOPS•