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UCD EEC 116 - Lecture #10 Memories

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EEC 116 Lecture #10: MemoriesAnnouncementsOutlineMemory and Performance Trend IMemory and Performance Trend IITypes of Memory ITypes of Memory IIMemory Usage in ComputersBasic Memory Array StructureMemory Circuit OperationDRAMDRAM Issues3T DRAM CellAdvanced DRAM ProcessROMSRAM CellSRAM Design: Read “0”SRAM Design: Read “0”SRAM Design: Read “0”SRAM Design: Write “0” (1st Analysis)SRAM Design: Write “0” (1st Analysis)SRAM Design: Write “0” (1st Analysis)SRAM Design: Write “0” (2nd Analysis)SRAM Design: Write “0” (2nd Analysis)SRAM Design: Write “0” (2nd Analysis)SRAM Static Noise MarginsHold Static Noise MarginRead Static Noise MarginWrite Static Noise MarginMemory PeripheralsFlash Memory Transistor With Floating GateFlash Memory OperationNext Topics: Low Power Circuits and LimitsAnnouncementsReview: Dynamic CMOSReview: Dynamic CMOS TradeoffsEEC 116 Lecture #10:MemoriesRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 116 Fall 2011 2Announcements• Work on Lab 5 this week• Quiz 3 Monday• Midterms back at end of classAmirtharajah/Parkhurst, EEC 116 Fall 2011 3Outline• Finish: Interconnect• Memories: Rabaey 12.1-12.2 (Kang & Leblebici, 10.1-10.6)Amirtharajah/Parkhurst, EEC 116 Fall 2011 4Memory and Performance Trend I• Memory is becoming a key factor in the performance of a computer• 1stgeneration computers had just system memory– Very slow DRAM– As microprocessors got faster, the bottleneck in performance was data access• 2ndgeneration computers added cache memory– This provided faster access to small localized memory that was being read or written• Memory placed on front side bus (off-chip)• Performance increased– As processors got faster memory access again became the bottleneckAmirtharajah/Parkhurst, EEC 116 Fall 2011 5Memory and Performance Trend II• 3rdgeneration computers added on chip cache– These caches started out 16K and were termed level 1 cache– Soon we had level 1 and level 2 cache– Currently we have three levels of cache on chip that run at processor frequency, then access main memory if data can’t be found in any of these caches– Moving to stacking memory die on top of processorAmirtharajah/Parkhurst, EEC 116 Fall 2011 6Types of Memory I• ROM: read-only memory– Non-volatile – mask programmed• RWM: read-write memory (RAM, random access memory)– SRAM: static memory• Data is stored as the state of a bistable circuit• State is retained without refresh as long as power is supplied– DRAM: dynamic memory• Data is stored as a charge on a capacitor• State leaks away, refresh is requiredAmirtharajah/Parkhurst, EEC 116 Fall 2011 7Types of Memory II• NVRWM: non-volatile read-write memory (also called NVRAM, non-volatile random access memory)– Flash (EEPROM): ROM at low voltages, writable at high voltages (Electrically Erasable Programmable Read-Only Memory)– EPROM: ROM, but erasable with UV light (falling out of common usage)Amirtharajah/Parkhurst, EEC 116 Fall 2011 8Memory Usage in Computers• DRAM Memory– Main memory storage. Used for data and programs• SRAM Memory– Faster than DRAM, however, uses more transistors• Used to be used for external cache• Variant used in internal cache (on chip cache)• FLASH Memory and ROM– Used for BIOS data storage in PCs– Also used to store pictures, MP3 files for digital cameras and MP3 players – eventually for hard diskAmirtharajah/Parkhurst, EEC 116 Fall 2011 9Basic Memory Array Structure• Memory cells arranged in a rectangular array• Rows correspond to data words– Accessed through a row decoder• Columns to individual bits– Selected through a column mux• Bit voltage amplified by sense amplifier00A112−k1012−−kN1A1−kA0D1DmDMemory Array 2Nbits()kN−1−NkAA KAmirtharajah/Parkhurst, EEC 116 Fall 2011 10Memory Circuit Operation• Wordlines (WL) control row (word) access– Usually control gates of pass transistors• Bitlines (BL) route column data (individual bits)– Bitlines usually precharged high (like dynamic logic)– Memory cells discharge bitline depending on stored data (bitline left high if cell stores 1, bitline discharged if cell stores 0)– Bitline swings usually small (10s – 100s of mV) and must be amplified by sense amplifiers– Synchronous or asynchronous timing can be used• Memory cellsstore data value– Static vs. dynamic, single or multiple bits, etc.Amirtharajah/Parkhurst, EEC 116 Fall 2011 11DRAM• Smaller cell size (1 transistor or 1T cell)– Reason for inexpensive memory in computers– Tradeoff of area (memory density) vs. speed and complexity (refreshing)BLWLQAmirtharajah/Parkhurst, EEC 116 Fall 2011 12DRAM Issues• Must be periodically refreshed– Reads are destructive (modify voltage stored on capacitor)– Every read followed by a refresh of the bit (write back of read value)• No static power dissipation• Output voltage is charge sharing result of storage capacitor and bitline capacitance– More complex sense amplifiers– Higher noise susceptibility• Requires different CMOS process than high performance logic– Not compatible with cache in microprocessorsAmirtharajah/Parkhurst, EEC 116 Fall 2011 133T DRAM CellReadStoreM3M1M23T DRAMWrite• Early DRAM technology• Gate cap of M1 stores bit• Nondestructive reads• Storage node voltage < VDD– Compensate with boosted wordlineBit LineAmirtharajah/Parkhurst, EEC 116 Fall 2011 14Advanced DRAM Process• Vertical transistor, trench capacitor (Beintner, JSSC 04)Amirtharajah/Parkhurst, EEC 116 Fall 2011 15BLWLQROM• Dotted lines refer to either set at ‘1’ or ‘0’– PROM: Replace dotted lines with fuses• Small cell size (1T cell)• Not necessary to refresh• No static power dissipation• Output voltage is set by WL durationEitherAmirtharajah/Parkhurst, EEC 116 Fall 2011 16SRAM Cell• Cross-coupled inverters: bistable element• Density is important in memories– Single NMOS pass transistor used for reading/writing– Transistor sizes should take up minimum area• Faster than DRAM since typically fewer cells• No refresh required (nondestructive reads)BL BLWLQQAmirtharajah/Parkhurst, EEC 116 Fall 2011 17SRAM Design: Read “0”• Prior to read operation, voltage at node Q = 0V and Q = Vdd, bit lines precharged to Vdd• Transistors M3 and M4 are turned on by word line (WL) select circuitryVdd VddWLQQM5M1


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