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UCD EEC 116 - Transmission Gate Logic

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EEC 116 Lecture: Transmission Gate LogicTransmission Gate LogicEquivalent Transmission Gate ResistanceEquivalent ResistanceResistance ApproximationsEquivalent Resistance – Region 1Equivalent Resistance – Region 2Equivalent Resistance – Region 3Transmission Gate LogicTransmission Gate XORTransmission Gate MultiplexerEEC 116 Lecture:Transmission Gate LogicRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 116 Fall 2011 2Transmission Gate Logic• NMOS and PMOS connected in parallel• Allows full rail transition – ratioless logic• Equivalent resistance relatively constant during transition• Complementary signals required for gates• Some gates can be efficiently implemented using transmission gate logic (XOR in particular)==Amirtharajah/Parkhurst, EEC 116 Fall 2011 3Equivalent Transmission Gate Resistance• For a rising transition at the output (step input)– NMOS sat, PMOS sat until output reaches |VTP|– NMOS sat, PMOS lin until output reaches VDD-VTN– NMOS off, PMOS lin for the final VDD–VTNto VDDvoltage swingVinVout= 0V @ t=0VDD0VAmirtharajah/Parkhurst, EEC 116 Fall 2011 4Equivalent Resistance• Equivalent resistance Reqis parallel combinatonof Req,nand Req,p• Reqis relatively constantVDDVTpVDD-VTnReq,pReq,nReqRVoutAmirtharajah/Parkhurst, EEC 116 Fall 2011 5Resistance Approximations• To estimate equivalent resistance:– Assume both transistors in linear region– Ignore body effect– Assume voltage difference (VDS) is small()tnDDnneqVVkR−≈1,()tpDDppeqVVkR−≈1,()()tpDDptnDDneqVVkVVkR−+−≈1Amirtharajah/Parkhurst, EEC 116 Fall 2011 6Equivalent Resistance – Region 1• NMOS saturation:• PMOS saturation:()()221,tnoutDDnoutDDneqVVVkVVR−−−=()()221,tpDDpoutDDpeqVVkVVR−−−=Amirtharajah/Parkhurst, EEC 116 Fall 2011 7Equivalent Resistance – Region 2• NMOS saturation:• PMOS linear:()()()()()()()[]outDDTPDDpoutDDoutDDTPDDpoutDDpeqVVVVkVVVVVVkVVR−−−=−−−−−=22222,()()221,tnoutDDnoutDDneqVVVkVVR−−−=Amirtharajah/Parkhurst, EEC 116 Fall 2011 8Equivalent Resistance – Region 3• NMOS cut off:• PMOS linear:∞=neqR,()()[]outDDTPDDppeqVVVVkR−−−=22,Amirtharajah/Parkhurst, EEC 116 Fall 2011 9Transmission Gate Logic• Useful for multiplexers (select between multiple inputs) and XORs• Transmission gate implements logic function F = A if S– If S is 0, output is floating, which should be avoided– Always make sure one path is conducting from input to output• Only two transmission gates needed to implement AS + AS– Transmission Gate 1: A if S– Transmission Gate 2: A if SAmirtharajah/Parkhurst, EEC 116 Fall 2011 10• If S = 0, F = A and when S = 1, F = ~ATransmission Gate XORSSASSSAF⊕=Amirtharajah/Parkhurst, EEC 116 Fall 2011 11Transmission Gate MultiplexerSSASBSSAF


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UCD EEC 116 - Transmission Gate Logic

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