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UCD EEC 116 - CMOS Inverter AC Characteristics

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EEC 116 Lecture #4: CMOS Inverter AC CharacteristicsAcknowledgmentsAnnouncementsOutlineCMOS Inverter VTC: Device OperationLogic Circuit DelayCMOS Inverter CapacitancesCMOS Inverter Junction CapacitancesCMOS Inverter Gate CapacitancesCMOS Inverter Capacitances: Miller EffectCMOS Inverter Capacitances: ReceiverInverter Capacitances: AnalysisFirst-Order Inverter DelayInverter Delay: FallingInverter Delay: FallingInverter Delay: Falling t1-t0Inverter Delay: Falling t2-t1Inverter Delay: Falling, TotalInverter Delay: RisingInverter Rise, Fall TimesCMOS Inverter DelayCMOS Inverter Delay: 2nd ApproximationCMOS Inverter Delay: Finite Input TransitionsHow to Improve Delay?Inverter Power ConsumptionNext Time: Combinational Logic and LayoutEEC 116 Lecture #4:CMOS Inverter AC CharacteristicsRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 116 Fall 2011 2Acknowledgments• Slides due to Rajit Manohar from ECE 547 Advanced VLSI Designat Cornell UniversityAmirtharajah/Parkhurst, EEC 116 Fall 2011 3Announcements• Lab 2 this week, report due next week• Quiz 1 on Monday!Amirtharajah/Parkhurst, EEC 116 Fall 2011 4Outline• Review: CMOS Inverter Transfer Characteristics• Finish Lecture 3 slides• CMOS Inverters: Rabaey 5.4-5.5 (Kang & Leblebici, 6.1-6.4, 6.7)Amirtharajah/Parkhurst, EEC 116 Fall 2011 5CMOS Inverter VTC: Device OperationP linearN cutoffP linearN satP satN satP satN linearP cutoffN linearAmirtharajah/Parkhurst, EEC 116 Fall 2011 6Logic Circuit Delay• For CMOS (or almost all logic circuit families), only one fundamental equation necessary to determine delay:• Consider the discretized version:• Rewrite to solve for delay:• Only three ways to make faster logic: C, ΔV, IdtdVCI =tVCIΔΔ=IVCtΔ=ΔAmirtharajah/Parkhurst, EEC 116 Fall 2011 7CMOS Inverter CapacitancesVinVddGndCgd,pCgs,pCdb,pCsb,pCgd,nCgs,nCsb,nCdb,nCintCgf• Assume input transition is fixed, then delay determined by outputCapacitance on node f (output):• Junction capCdb,p and Cdb,n• Gate capacitanceCgd,p and Cgd,n• Interconnect cap• Receiver gate capAmirtharajah/Parkhurst, EEC 116 Fall 2011 8CMOS Inverter Junction Capacitances• Junction capacitances Cdb,pand Cdb,n:– Equation for junction cap:– Non-linear, depends on voltage across junction–Use Keqfactor to get equivalent capacitance for a voltage transition()mdadajmjjNNNNqCVACVC⎟⎟⎠⎞⎜⎜⎝⎛+=⎟⎟⎠⎞⎜⎜⎝⎛−=000012,1φεφjsweqswjeqdbCPKCAKC+=Amirtharajah/Parkhurst, EEC 116 Fall 2011 9CMOS Inverter Gate Capacitances• Gate capacitances CGD,pand CGD,n:– Just after the input switches(t = 0+), what regions are transistors in?– One is in cutoff: CGD= Overlap Cap– One is in Saturation: CGD= Overlap Cap– Therefore, gate-to-drain capacitance is due to overlap capacitance :DoxngdpgdWLCCC==,,However, also need to consider Miller effect ...Amirtharajah/Parkhurst, EEC 116 Fall 2011 10CMOS Inverter Capacitances: Miller Effect• When input rises by ΔV, output falls by ΔV– Change in stored charge: ΔQ = Cgd1ΔV – (-Cgd1ΔV)– Effective voltage change across Cgd1is 2ΔV– Effective capacitance to ground is twice Cgd1• Including Miller effect:VinVoutCgd1VinVout2Cgd1DoxngdpgdWLCCC 2,,==(For transistor in Cutoff)Amirtharajah/Parkhurst, EEC 116 Fall 2011 11CMOS Inverter Capacitances: Receiver• Receiver gate capacitance– Includes all capacitances of gate(s) connected to output node– Unknown region of operation for receiver transistor: total gate cap varies from (2/3)WLCoxto WLCox– Ignore Miller effect (taken into account on output)– Assume worst-case value, include overlapoxDoxeffgCWLCWLC 2+=Cg= WL CoxAmirtharajah/Parkhurst, EEC 116 Fall 2011 12Inverter Capacitances: Analysis• Simplify the circuit: combine all capacitances at output into one lumped linear capacitance:Cload= 2*Cgd,n + 2*Cgd,p + Cdb,n + Cdb,p + Cint+ Cg• Csb,n = Csb,p = 0• Cgs,n and Cgs,p are not connected to the load. These are part of the gate capacitance CgMiller effectAmirtharajah/Parkhurst, EEC 116 Fall 2011 13First-Order Inverter Delay• Suppose ideal voltage step at input• Assume: Current charging or discharging capacitance Cloadis nearly constant Iavg• tPHL= Cload(Vdd - Vdd/2) / Iavg• tPLH= Cload(Vdd/2 - Vss) / IavgVinVoutCloadAmirtharajah/Parkhurst, EEC 116 Fall 2011 14ID.nInverter Delay: Falling• Assume PMOS fully off (ideal step input, ID,p= 0)CloadVindtdVCIdtdVCIoutloadnD==,Need to determine ID,nAmirtharajah/Parkhurst, EEC 116 Fall 2011 15Inverter Delay: Falling• From t0to t1: NMOS in saturation• From t1to t2: NMOS in linear region• Find IDin each regionVddVdd - VtnVdd/2t0t1t2NMOS in saturationNMOS in linear regionAmirtharajah/Parkhurst, EEC 116 Fall 2011 16Inverter Delay: Falling t1-t0• Assumption: Input fast enough to go through transition before output voltage changes• Voutdrops from VOHto VDD-VTN(NMOS saturated)2,0,0012,02,02,0)(2)(22/)(2/)(,010nTOHnnTLVVVoutnTOHnLttnTOHnnTinnDSVVkVCttdVVVkCdtVVkVVkInTOHOH−=−−−=−=−=∫∫−Amirtharajah/Parkhurst, EEC 116 Fall 2011 17Inverter Delay: Falling t2-t1• Voutdrops from (VOH-VT0,n) to VDD/2• NMOS in linear region[][]⎥⎦⎤⎢⎣⎡++−−−=−−−−=−−−=∫+−2/)(2/)()(2ln)()()(,0,0122/)(221,012221,0,0OLOHOLOHnTOHnTOHnLVVVVoutoutnTOHnoutLoutoutnTOHnDSVVVVVVVVkCttVVVVkdVCttVVVVkIOLOHnTOHAmirtharajah/Parkhurst, EEC 116 Fall 2011 18Inverter Delay: Falling, Total• Total fall delay = (t1-t0) + (t2-t1)⎥⎦⎤⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−+−+−−= 1)(4ln2)(,0,0,0,0 OLOHnTOHnTOHnTnTOHnLPHLVVVVVVVVVkCtAmirtharajah/Parkhurst, EEC 116 Fall 2011 19Inverter Delay: Rising• Similar calculation as for falling delay• Separate into regions where PMOS is in linear, saturation• Note: to balance rise and fall delays (assuming VOH= VDD, VOL= 0V, and VT0,n=VT0,p) requires5.2≈=⎟⎠⎞⎜⎝⎛⎟⎠⎞⎜⎝⎛pnnpLWLWμμ⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−+−−+−−−−= 1)(4ln2)(,0,0,0,0OLOHpTOLOHpTOLOHpTpTOLOHpLPLHVVVVVVVVVVVVkCt1=npkkAmirtharajah/Parkhurst, EEC 116 Fall 2011 20Inverter Rise, Fall Times• Summary -- Exact method: separate into two regions–t1•Voutdrops from 0.9VDDto VDD-VT,n(NMOS in saturation)•Voutrises from 0.1VDDto |VT,p| (PMOS in saturation)–t2•Voutdrops from VDD-VT,nto 0.1VDD(NMOS in linear region)•Voutrises from |VT,p| to 0.9 VDD(PMOS in linear region)–tf,r= t1+ t2Amirtharajah/Parkhurst, EEC 116 Fall


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