1INTRODUCTION TO FULL-CUSTOM LAYOUTEEC116,Winter2010,B.Baas463D PerspectivePolysiliconAluminumSource: Digital Integrated Circuits, 2nd ©2EEC116,Winter2010,B.Baas47CMOS ProcessSource: Digital Integrated Circuits, 2nd ©EEC116,Winter2010,B.Baas48A Modern CMOS Processp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS ProcessSource: Digital Integrated Circuits, 2nd ©3EEC116,Winter2010,B.Baas49nwell and pwell•The“bodies”ofthetransistorsSource: Omar Sattari EEC116,Winter2010,B.Baas50ndiffusion and pdiffusion• SourceandDrainforeachtransistorSource: Omar Sattari4EEC116,Winter2010,B.Baas51Polysilicon• Gateoftransistorsandforshort‐distancewiringSource: Omar Sattari EEC116,Winter2010,B.Baas52metal1•FirstlevelofinterconnectSource: Omar Sattari5EEC116,Winter2010,B.Baas53metal2•SecondlayerofinterconnectSource: Omar Sattari EEC116,Winter2010,B.Baas54Building an Inverter: Starting with Well and Diffusion•PlaceN‐typeandP‐typediffusions–ConventionistoplacePMOSontopandNMOSonbottomSource: Omar Sattari6EEC116,Winter2010,B.Baas55Transistors•polycrossingdiffusionproducesatransistor!• Commongatehere•PMOSshownontop•NMOSshownonbottomSource: Omar Sattari EEC116,Winter2010,B.Baas56metal1• metal1laiddownbutnotyetconnected•UsemetalforVddandGnd• Labelsadded– Extremelyusefulfortesting–Documentsdesign–Use“point”labels,notlargeareaones– Neverusegloballabelsthatendinan“!”Source: Omar Sattari7EEC116,Winter2010,B.Baas57metal1 contacts• Connectionsnowmadebetweenmetal1and:–pdiff–ndiff–poly–nwell–pwell• Eachvia/contactisadifferentlayerinmagicSource: Omar Sattari EEC116,Winter2010,B.Baas58metal2•Usemetal2forlongerdistancerouting•Routesoverthe“top” ofothercircuitsshown• metal2contactsconnectmetal1andmetal2onlySource: Omar Sattari8EEC116,Winter2010,B.Baas59MOSIS•Low‐costVLSIprototypingandsmall‐volumeproductionservice• AffiliatedwithInformationSciencesInstituteatUSCinMarinadelRey,California•Since1981,theyhavefabricatedmorethan50,000circuitdesignsforcommercialfirms,governmentagencies,andresearchandeducationalinstitutions• Traditionallyhasbeenbestplaceforsupportofmagicanddesignrules–Changingsomewhatrecently•CMPprovidessameservices,basedinFranceEEC116,Winter2010,B.Baas60Design Rules•Interfacebetweendesignerandprocess(CMOSfabrication)engineer• Guidelinesforconstructingfabricationmasks•Unitscommonlyused–scalabledesignrules:lambda(λ)parameter(usedinmagic),or–absolutedimensions(micronrules)• Commonruleexamples:– minimumwidth– minimumseparationsamematerial– minimumseparationdifferentmaterial• Lookforwhitedotsinmagicthatshowerrors9EEC116,Winter2010,B.Baas61Design Rules•MeadandConway,1980– “Lambda‐based” scalabledesignrules– Allowsfull‐customdesignstobeeasilyreusedfromtechnologygenerationtotechnologygeneration–Lambdaisroughlyonehalftheminimumfeaturesize• “1.0μmtechnology” ‐>1.0μmmin.length,lambda=0.5μm• “0.5μmtechnology” ‐>0.5μmmin.length,lambda=0.25μm–Forourclass,weareusinga0.18μmtechnologysolambdais0.09μm•SeecoursewebsiteforlinktoourscalabledesignrulesontheMOSISwebsite•Weareusing“SCMOS_DEEP” rulesEEC116,Winter2010,B.Baas62Example Intra-Layer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleSource: Digital Integrated Circuits, 2nd ©10EEC116,Winter2010,B.Baas63Example Design Rules:Transistor Layout1253TransistorSource: Digital Integrated Circuits, 2nd ©EEC116,Winter2010,B.Baas64Example Design Rules: Vias and Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322Source: Digital Integrated Circuits, 2nd ©11EEC116,Winter2010,B.Baas65Design Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.In magic, white dots appearat the point of a DRC ruleviolationSource: Digital Integrated Circuits, 2nd ©Place a box around whitedots and press “y” to see what is causing an