FABRICATION Primary Chip Ingredients Silicon crystalline SiO2 Silicon polycrystalline poly polysilicon n type dopants p type dopants Metal wires Contacts vias EEC 116 Spring 2007 B Baas red 31 1 Primary Fabrication Ingredients and Processes Photoresist Positive photoresist becomes soluble when exposed to light Negative photoresist becomes insoluble when exposed to light Applied roughly 1 um thick to entire wafer Etching processes Acid wet etching HF acid Plasma dry etching Masks one per patterned shape Laying down material Deposition CVD Growth Implantation ion implantation and diffusion implantation Implanting a material into the substrate Sputtering for metals Planarization extreme flattening of the wafer s surface EEC 116 Spring 2007 B Baas 32 Primary Fabrication Ingredients and Processes Producing High Dopant Concentration Regions Source drains transistor channels well and substrate contacts polysilicon Diffusion implantation Silicon exposed to dopant gas at high temperature Ion implantation Dopant ions are implanted at high speed with an accelerator Causes lattice damage Normally followed by annealing step short high temperature crystal healing process EEC 116 Spring 2007 B Baas 33 2 Basic repeated process Deposit a material Coat with photoresist Expose photoresist to a pattern of UV light using a light source and a patterned mask Remove soluble photoresist with selective etching Remove material below photoresist with selective etching base material only Remove remaining photoresist with selective etching hardened photoresist only 34 EEC 116 Spring 2007 B Baas Photo Lithographic Process Overview optical mask oxidation photoresist removal ashing photoresist coating stepper exposure Typical operations in a single photolithographic cycle from Fullman photoresist development acid etch process step EEC 116 Spring 2007 B Baas spin rinse dry Source Digital Integrated Circuits 2nd 35 3 Etching of Polysilicon EEC 116 Spring 2007 B Baas Source Device Electronics for Int Circuits 36 MASKS 4 magic Layers vs Mask Layers magic allows designers to work with logical layers Chip fabrication requires more detailed layers magic captures all necessary information and generates the rest 38 EEC 116 Spring 2007 B Baas FABRICATION 3 EXAMPLES 5 Fabrication Example 1 The example shows a 2 D side view of the fabrication steps for the following A single NMOS transistor Metal1 contacts Metal1 layer 40 EEC 116 Spring 2007 B Baas Fabrication Patterning of SiO2 Grow SiO2 on Si by exposing to O2 high temperature accelerates this process Cover surface with photoresist PR Sensitive to UV light wavelength determines feature size Positive PR becomes soluble after exposure Negative PR becomes insoluble after exposure EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 41 6 Fabrication Patterning of SiO2 Photoresist removed with a solvent SiO2 removed by etching HF Remaining photoresist removed with another solvent EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 42 NMOS Transistor Fabrication Thick field oxide grown Field oxide etched to create area for transistor Gate oxide high quality grown EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 43 7 NMOS Transistor Fabrication Polysilicon deposited doped to reduce R Polysilicon etched to form gate Gate oxide etched from source and drain Self aligned process because source drain aligned by gate Si doped with donors to create n regions EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 44 NMOS Transistor Fabrication Insulating SiO2 grown to cover surface gate Source Drain regions opened Aluminum evaporated to cover surface Aluminum etched to form metal1 interconnects EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 45 8 Fabrication Example 2 The example shows a 3 D view of the fabrication steps for the following A CMOS inverter A single NMOS transistor A single PMOS transistor Metal1 contacts Metal1 layer EEC 116 Spring 2007 B Baas 46 Inverter Fabrication Inverter Logic symbol CMOS inverter circuit CMOS inverter layout top view of lithographic masks EEC 116 Spring 2007 B Baas 47 9 Inverter Fabrication N wells created Thick field oxide grown surrounding active regions Thin gate oxide grown over active regions EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 48 Inverter Fabrication Polysilicon deposited Chemical vapor deposition Places the Poly Dry plasma etch Removes unwanted Poly EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 49 10 Inverter Fabrication N and P regions created using two masks Source Drain regions Substrate contacts EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 50 Inverter Fabrication Insulating SiO2 deposited using CVD Source Drain Substrate contacts exposed EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 51 11 Inverter Fabrication Metal Al deposited using evaporation Meta1 contacts made with Aluminum here Metal patterned by etching EEC 116 Spring 2007 B Baas Source CMOS Digital Integrated Circuits 52 Fabrication Example 3 The example shows a 2 D side view of the fabrication steps for the following A CMOS inverter A single NMOS transistor A single PMOS transistor Metal1 contacts Metal1 layer Metal2 vias Metal2 EEC 116 Spring 2007 B Baas 53 12 CMOS Process Walk Through p epi a Base material p substrate with p epi layer p SiN 34 SiO 2 p epi b After deposition of gate oxide and sacrificial nitride acts as a buffer layer p c After plasma etch of insulating trenches using the inverse of the active area mask p EEC 116 Spring 2007 B Baas Source Digital Integrated Circuits 2nd 54 CMOS Process Walk Through SiO 2 d After trench filling CMP planarization and removal of sacrificial nitride n p EEC 116 Spring 2007 B Baas e After n well and V adjust implants Tp f After p well and V adjust implants Tn Source Digital Integrated Circuits 2nd 55 13 CMOS Process Walk Through poly silicon g After polysilicon deposition and etch n p h After n source drain and p source drain implants These steps also dope the polysilicon SiO 2 i After deposition of SiO insulator and contact hole2etch EEC 116 Spring 2007 B Baas Source Digital Integrated Circuits 2nd 56 CMOS Process Walk Through Al j After deposition and patterning of first Al layer Al SiO 2 k After deposition of SiO insulator etching of via s 2 deposition and patterning of second layer of Al EEC 116 Spring 2007 B Baas Source Digital Integrated Circuits 2nd 57 14