EEC 116 Lecture: Hardware Description LanguagesAnnouncementsOutlineHardware Description LanguagesHDL and SimulationHardware Description StylesVerilog Simulation EnvironmentVerilog Example: 4b Adder Verilog Example: 4b Adder (cont.)Verilog Example: 4b Adder (cont.)Verilog Example: 4b Adder (cont.)Verilog Example: 4b Adder (cont.)Verilog Example: 4b Adder (cont.)SummaryOther Verilog Resources Next Topic: Analog Design Verilog Example: 4b Adder (cont.)EEC 116 Lecture:Hardware Description LanguagesRajeevan AmirtharajahUniversity of California, DavisAmirtharajah, EEC 116 Fall 2011 3Outline• Announcements• HDL Overview• A Verilog ExampleAmirtharajah, EEC 116 Fall 2011 4Hardware Description Languages• HDL: Language for capturing behavior and/or implementation of digital (sometimes analog or mixed-signal) hardware– Don’t think of it as a programming language…– …because concurrency (parallelism) is inherent!– Assuming sequential execution of statements can mislead you into bugs or poor synthesized hardware• Design Process– Begin by planning hardware– Write code that implies that hardware to synthesis tool• Two major languages: VHDL and Verilog– Will use Verilog in EEC119ABAmirtharajah, EEC 116 Fall 2011 5HDL and Simulation• A simulator that implements the event-driven semantics of an HDL is needed to evaluate Verilogcode.–Verilog-XL(Cadence): interpreted simulator; well-integrated but slow (esp. for large designs)– NC_Verilog (Cadence): compiled simulator; translates Verilog to C and compiles C to executable. Startup slow but execution fast.–VCS(Synopsys): compiled simulator; fast, but not integrated with Cadence• All simulators can be run standalone from command line for HDL-only designs.Amirtharajah, EEC 116 Fall 2011 6Hardware Description Styles• Two general styles for capturing hardware description• Structural– Modules composed of simpler modules or primitives (gates, transistors)– Describes a circuit schematic or netlist• Behavioral– Describes how outputs are computed as function of inputs– Incorporates high-level programming language constructs (loops, if-then-else statements, case statements)– Behavioral descriptions can be synthesized to structuralAmirtharajah, EEC 116 Fall 2011 7Verilog Simulation EnvironmentModule “test”Instance “top”Verilog netlistmodule (DUT)Testbench code“initial” blockDUT inputsDUT outputsAmirtharajah, EEC 116 Fall 2011 8Verilog Example: 4b Adder Time Units“test” Module WrapperSignal Declarations“top” Module InstanceTestbench Code FileCarry OutSumOutputs declared as type wire.Carry InSummandsInputs declared as type reg.Amirtharajah, EEC 116 Fall 2011 9Verilog Example: 4b Adder (cont.)“adder 4b” Module DeclarationSignal DeclarationsParameter DefinitionsStructural DescriptionAmirtharajah, EEC 116 Fall 2011 10Verilog Example: 4b Adder (cont.)“FullAdder” Module DeclarationSignal DeclarationsParameter DefinitionsStructural DescriptionAmirtharajah, EEC 116 Fall 2011 11Verilog Example: 4b Adder (cont.)Initialization of register signalsInteger DeclarationsUseful console messagesNested for loops to generate input vectors and test output results.Amirtharajah, EEC 116 Fall 2011 12Verilog Example: 4b Adder (cont.)Print inputs and outputsCheck output against calculationPrint error if mismatchToggle Carry InIncrement BIncrement AAmirtharajah, EEC 116 Fall 2011 13Verilog Example: 4b Adder (cont.)Behavioral Verilogcode!Amirtharajah, EEC 116 Fall 2011 14Summary• Think about hardware when coding HDL!– Initial module development using behavioral code– Translated to structural code, schematic, layout as design proceeds• Testbench implemented using behavioral code –doesn’t change– Write once, use many times, so worth it to design well• Test each refinement of design using same testbench(Regression Testing)– Catch bugs at each step of design processAmirtharajah, EEC 116 Fall 2011 15Other Verilog Resources • H. Wang, “Introduction to Verilog Hardware Description Language”, PDF slides on SmartSite• Aldec, Inc., Verilog Interactive Tutorial (AldecVerilogEvita.exe)– Windows executable on SmartSite; no warranty and standard disclaimer applies• Weste and Harris, “CMOS VLSI Design”, 3rd. ed., Appendix A.• … many other resources on the