1FABRICATION3 EXAMPLESEEC116,Winter2010,B.Baas21Fabrication Example 1•Theexampleshowsa2‐Dsideviewofthefabricationstepsforthefollowing–AsingleNMOStransistor– Metal1contacts– Metal1layer2EEC116,Winter2010,B.Baas22Fabrication – Patterning of SiO2•GrowSiO2onSibyexposingtoO2–hightemperatureacceleratesthisprocess•Coversurfacewithphotoresist(PR)–SensitivetoUVlight(wavelengthdeterminesfeaturesize)–PositivePRbecomessolubleafterexposure– NegativePRbecomesinsolubleafterexposureSource: CMOS Digital Integrated Circuits EEC116,Winter2010,B.Baas23Fabrication – Patterning of SiO2• Photoresistremovedwithasolvent•SiO2removedbyetching(HF)•RemainingphotoresistremovedwithanothersolventSource: CMOS Digital Integrated Circuits3EEC116,Winter2010,B.Baas24NMOS Transistor Fabrication•Thickfieldoxidegrown• Fieldoxideetchedtocreateareafortransistor• Gateoxide(highquality)grownSource: CMOS Digital Integrated Circuits EEC116,Winter2010,B.Baas25NMOS Transistor Fabrication• Polysilicondeposited(dopedtoreduceR)• Polysiliconetchedtoformgate•Gateoxideetchedfromsourceanddrain–Self‐alignedprocessbecausesource/drainalignedbygate•Sidopedwithdonorstocreaten+regionsSource: CMOS Digital Integrated Circuits4EEC116,Winter2010,B.Baas26NMOS Transistor Fabrication•InsulatingSiO2growntocoversurface/gate• Source/Drainregionsopened•Aluminumevaporatedtocoversurface•Aluminumetchedtoformmetal1interconnectsSource: CMOS Digital Integrated Circuits EEC116,Winter2010,B.Baas27Fabrication Example 2•Theexampleshowsa3‐Dviewofthefabricationstepsforthefollowing–ACMOSinverter•AsingleNMOStransistor•AsinglePMOStransistor– Metal1contacts– Metal1layer5EEC116,Winter2010,B.Baas28Inverter Fabrication•Inverter–Logicsymbol–CMOSinvertercircuit–CMOSinverterlayout(topviewoflithographicmasks)EEC116,Winter2010,B.Baas29Inverter Fabrication•N‐wellscreated•Thickfieldoxidegrownsurroundingactiveregions•ThingateoxidegrownoveractiveregionsSource: CMOS Digital Integrated Circuits6EEC116,Winter2010,B.Baas30Inverter Fabrication• Polysilicondeposited–Chemicalvapordeposition(PlacesthePoly)–Dryplasmaetch(RemovesunwantedPoly)Source: CMOS Digital Integrated Circuits EEC116,Winter2010,B.Baas31Inverter Fabrication•N+andP+regionscreatedusingtwomasks– Source/Drainregions–SubstratecontactsSource: CMOS Digital Integrated Circuits7EEC116,Winter2010,B.Baas32Inverter Fabrication•InsulatingSiO2depositedusingCVD• Source/Drain/SubstratecontactsexposedSource: CMOS Digital Integrated Circuits EEC116,Winter2010,B.Baas33Inverter Fabrication•Metal(Al)depositedusingevaporation–Meta1contactsmadewithAluminumhere•MetalpatternedbyetchingSource: CMOS Digital Integrated Circuits8EEC116,Winter2010,B.Baas34Fabrication Example 3•Theexampleshowsa2‐Dsideviewofthefabricationstepsforthefollowing–ACMOSinverter•AsingleNMOStransistor•AsinglePMOStransistor– Metal1contacts– Metal1layer– Metal2vias– Metal2EEC116,Winter2010,B.Baas35CMOS Process Walk-Throughp+p-epi(a) Base material: p+ substrate with p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)Source: Digital Integrated Circuits, 2nd ©9EEC116,Winter2010,B.Baas36CMOS Process Walk-ThroughSiO2(d) After trench filling, CMPplanarization, and removal of sacrificial nitride(e) After n-well and VTpadjust implantsn(f) After p-well andVTnadjust implantspSource: Digital Integrated Circuits, 2nd ©EEC116,Winter2010,B.Baas37CMOS Process Walk-Through(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO2Source: Digital Integrated Circuits, 2nd ©10EEC116,Winter2010,B.Baas38CMOS Process Walk-Through(j) After deposition and patterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2Source: Digital Integrated Circuits, 2nd ©ADVANCED METAL INTERCONNECT EXAMPLES11EEC116,Winter2010,B.Baas40Four Levels of Metal ExampleSource: Digital Integrated Circuits, 2nd ©EEC116,Winter2010,B.Baas41Advanced MetallizationSource: Digital Integrated Circuits, 2nd ©12EEC116,Winter2010,B.Baas42MicroprocessorInterconnectSource: IBM• Futuremicroprocessorinterconnect•8levelsofmetal• SteadilyincreasingpitchandthicknesswithhigherlevelsforhigherperformanceSource: ITRS Interconnect, 2005 m8m7m6m5m4m3m2m1EEC116,Winter2010,B.Baas43ASIC InterconnectSource: IBM• FutureApplicationSpecificIC(ASIC)interconnect•8levelsofmetal•Moreregularstructure–Semi‐globalis2xIntermediatepitch–Globalis4xIntermediatepitchSource: ITRS Interconnect, 2005 m7m6m5m4m3m2m8m113EEC116,Winter2010,B.Baas44IBM90 nmSource: