1VLSI FABRICATIONEEC116,Winter2010,B.Baas5Primary Chip Ingredients I1) Silicon– crystalline–Near‐perfectcrystal(atomsorganizedinaregular,orderedlattice)– Semiconductor—notaconductororinsulator,butsomewhereinbetweenanditsconductioncanbealteredsignificantly2) SiO2– Silicondioxide–Justlikeitsays,madefromsiliconandoxygen–Insulator3) Silicon–polycrystalline,poly,polysilicon– Siliconbutonlysmallregionsareorganizedascrystallinestructures.Polysiliconstructuresaremadeupofmultiplesmallcrystallineregionswherethesmallerregionsarenotalignedwitheachother.4) n‐typedopants– Materialsthatcontain5outerelectrons–“donors”– Examples:phosphorus,arsenic2EEC116,Winter2010,B.Baas6Primary Chip Ingredients II5) p‐typedopants– Materialsthatcontain3outerelectrons– “acceptors”– Examples:boron,gallium6) Metalwires–Inoldertechnologies,madeofaluminum.Nowcopperiscommonlyusedbecauseofitslowerresistivity.–Conductors7) Contacts/vias–Tungstenandaluminium commonlyused–Theseare“vertical” connectionsbetweenlayersEEC116,Winter2010,B.Baas7Primary Fabrication Ingredients and Processes I1) Photoresist• Positivephotoresist(becomessolublewhenexposedtoUVlight)• Negativephotoresist(becomesinsolublewhenexposedtoUVlight)• Appliedroughly1μmthicktoentirewafer2) Etchingprocesses•The“selectivity” ofdifferentetchesvariesinthesensethatthematerialsthatareetchedornotetcheddependsontheparticularetch.•Acid(wetetching).Ex:HFacid•Plasma(dryetching)3) Masks–oneperpatternedshape3EEC116,Winter2010,B.Baas8Primary Fabrication Ingredients and Processes II4) LayingdownmaterialA. Deposition•Examplemethod:CVD•Examplematerials:SiO2,siliconB. Growth•Examplematerials:SiO2onsiliconsubstrateC. Implantation•Produceshighdopant concentrationregions• Diffusionimplantation– Siliconexposedtodopant gasathightemperature•Ionimplantation– Dopant ionsareimplantedathighspeedwithanaccelerator–Causeslatticedamage– Normallyfollowedbyannealingstep(shorthightemperature“crystalhealing” process)•Exampleimplantedstructures:source/drains,transistorchannels,wellandsubstratecontacts,polysiliconD. Sputtering–formetalsEEC116,Winter2010,B.Baas9Primary Fabrication Ingredients and Processes III5) Planarization–extremeflatteningofthewafer’ssurface• Supposewehavethecasebelowwheresimilarpatternsstackedontopofeachotherproducelargeverticalfeaturespsubstratem1m2SiO2Idealsubstratepm1m2Cracks more easily and has higher resistanceWithout planarizationSiO24EEC116,Winter2010,B.Baas10Primary Fabrication Ingredients and Processes III5) Planarization–extremeflatteningofthew afer’ssurface•CMP:ChemicalMechanicalPlanarization(orPolishing)• Neededforreliabilityandconsistentthicknessofalargenumberofinterconnectlayerspsubstratesubstratem1m2SiO2pm1m2Cracks more easily and has higher resistanceIdeal Without planarizationSiO2EEC116,Winter2010,B.Baas11Basic repeated process1) Depositamaterial2) Coatwithphotoresist3) ExposephotoresisttoapatternofUVlightusingalightsourceandapatternedmask4) Removesolublephotoresistwithselectiveetching5) Removematerialbelowphotoresistwithselectiveetching(basematerialonly)6) Removeremainingphotoresistwithselectiveetching(hardenedphotoresistonly)5EEC116,Winter2010,B.Baas12oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresist stepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).Photo-Lithographic Process OverviewSource: Digital Integrated Circuits, 2nd
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