EEC 116 Fall 2011 Homework #4Rajeevan AmirtharajahDept. of Electrical and Computer EngineeringUniversity of California, DavisIssued: October 19, 2011Due: October 26, 2011, 4 PM in 2131 Kemper.Reading: Rabaey Chapters 6.2 and 7.1-7.3 [1].Reference: Kang and Leblebici Chapters 7 and 8 [2].For all problems in this homework assignment, assume we are using enhancement-typeNMOS and PMOS transistors which have the characteristics shown in Table 1, unless oth-erwise specified. Also, assume minimum length devices unless otherwise specified.Parameter NMOS PMOSVT 00.6 V -0.7 VµCox300 µA/V2100 µA/V2γ 0 0Lmin0.180µm 0.180µmλ 0.0 V−10.0 V−1VDD1.8 VTable 1: Assumed Transistor Parameters.1 Transparent LatchFor this problem, use the device parameters in Table 1. Assume that all PMOS devices haveW/L = 1.44µm/0.180µm and all NMOS devices have W/L = 0.450µm/0.180µm.Problem 1.1 Redraw the schematic of Figure 1 and label the D, clk, clk, and Q signals onthe schematic such that the circuit operates as a static positive transparent latch.Problem 1.2 Ignoring the feedback circuit in Figure 1, find the low to high propagationdelay tpLHfrom the input to the output assuming all inputs switch simultaneously usingthe average current method. Use at least two appropriate points in the output transitionto compute the average current. Assume for the inverter that tpLH= tpHL= 45 ps, idealvoltage steps for the inputs, and that there is no capacitance other than C0.1Figure 1: Transparent Latch.Problem 1.3 Find the high to low propagation delay tpHLfrom the input to the outputusing the same approach and making the same assumptions as in Problem 1.2.Problem 1.4 Suppose a negative edge-triggered flip-flop uses the latch of Figure 1 as itsmaster stage latch. What is a reasonable estimate of the setup time tsetupof the flip-flop?2 Flip-FlopFor this problem, use the device parameters in Table 1.Problem 2.1 Figure 2 shows the schematic for a positive edge-triggered flip-flop with anactive-low clear. Is this a synchronous or an asynchronous clear? Justify your answer.Problem 2.2 Find the switching threshold voltage VMfor the output inverter N5/P5. Isthe switching threshold for the C2MOS latch formed by transistors P1, P2, N1, and M2different? Why or why not?Problem 2.3 Calculate the clock-to-Q delay tCQfor a high-to-low transition on the outputQ using the average current method. Assume the setup time constraint is met and that theclock has an infinitely fast transition at each edge. Use the average current method outlinedin Problem 1.2 and assume a transistor with dimensions 1.4/0.6 has a gate capacitance toground (i.e., ignore the Miller effect) of 15fF and a source/drain capacitance of 10fF.2Figure 2: Flip-Flop. All dimensions in microns.3 Mixed Combinational and Sequential LogicProblem 3.1 A useful trick for highly optimized logic design is to fold a combinationalCMOS circuit into a sequential circuit such as a latch. Modify the master stage latch circuitshown in Figure 7-26 in Rabaey to incorporate the logic function F = A · (B + C). Size thetransistors such that the pullup and pulldown networks for the equivalent inverter have equalrise and fall times. Assume the mobility ratio µn/µp= 2.5, VT 0,n= |Vt0,p|, and a minimumsized device has W/L = 5/1. Write your answer in terms of the W/L ratios for the PMOSand NMOS devices. Hint: See Figure 7-31.References[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc.,