EEC 116 Lecture #6: Sequential LogicAnnouncementsOutlineSequential Logic Basic DefinitionSequential Logic Example: Mealy FSMPositive Feedback: Bistability MetastabilityBistable ElementsSet-Reset (SR) LatchSR LatchOther LatchesLatch CircuitsPositive Dynamic Transmission Gate Latch Transmission Gate Positive Static Latch Positive Static Latch Timing DiagramNMOS Pass Gate Positive Static Latch Master-Slave Flip-FlopEdge-Triggered Flip-Flops“Safest” Edge-Triggered Flip-Flop Edge-Triggered Flip-Flop Timing DiagramDynamic Positive Edge-Triggered FF Clocked Circuit TimingFlip-Flop: Timing DefinitionsMaximum Clock FrequencyStaticized Dynamic Positive Edge-Triggered FF Clock Overlap Failures Race Through and Feedback PathsNonoverlapping Clocks Methodology C2MOS Edge Triggered Flip-Flop Zero-Zero Overlap Condition High-High Overlap Condition C2MOS Design PipeliningNext Topic: Latchup and Layout Guidelines Next Topic: Logical Effort Staticized Dynamic Positive Edge-Triggered FF AnnouncementsEEC 116 Lecture #6:Sequential LogicRajeevan AmirtharajahUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah/Parkhurst, EEC 116 Fall 2011 2Announcements• Lab 3 extended, same due date as Lab 4• HW4 issued todayAmirtharajah/Parkhurst, EEC 116 Fall 2011 3Outline• Review: Arithmetic• Finish Transmission Gate Circuits and Multipliers• Sequential MOS Logic Circuits: Rabaey, 7.1-7.3 (Kang & Leblebici, 8.1-8.5)• Next Topic: Latchup and Layout GuidelinesAmirtharajah/Parkhurst, EEC 116 Fall 2011 4Sequential Logic Basic Definition• Combinational circuits’ output is a function of the circuit inputs and a delay time– Examples: NAND, NOR, XOR, adder, multiplier• Sequential circuits’ output is a function of the circuit inputs, previous circuit state, and a delay time– Examples: Latches, flip-flops, FSMs, pipelined adders and multipliers, microprocessors– Sequential elements are critical to implementing techniques such as feedback or blocks such as memoryAmirtharajah/Parkhurst, EEC 116 Fall 2011 5Sequential Logic Example: Mealy FSMLOGICtp,combΦIn Out• Two information storage mechanisms– Positive feedback-based (static) circuits– Charge storage-based (dynamic) circuits• Clock signal Φ controls timing of state (memory) updatesAmirtharajah/Parkhurst, EEC 116 Fall 2011 6Positive Feedback: Bistability 1iV21 ioVV=2oV21 oiVV=A21 oiVV=12 oiVV =C (metastable)BAmirtharajah/Parkhurst, EEC 116 Fall 2011 7δδMetastabilityGain should be larger than 1 in the transition regionACBVi1=Vo2Vo1=Vi2ACBVi1=Vo2Vo1=Vi2Amirtharajah/Parkhurst, EEC 116 Fall 2011 8Bistable Elements• Bistable elements have two stable states or operation modes• Cross-coupled inverters are the most basic bistableelement– Circuit forms the basis of latches and SRAM memory– Stable points on the VTC are those with the lowest energy– Points with high energy are unstable, perturbations are amplifiedAmirtharajah/Parkhurst, EEC 116 Fall 2011 9• Change inverters to NAND or NOR gates, with second inputs = S(set) and R(reset)• Allows control of the state of the bistable element• One input state is not allowed• Gating S and R with the clock prevents the latch from responding except during one phase of the clock cycleSet-Reset (SR) LatchSRQQSRQQAmirtharajah/Parkhurst, EEC 116 Fall 2011 10SR Latch• Sequential circuits: circuits which “store state”: circuits with memory elements• Latches: store previous output value for certain input combinations• SR latch (NAND-based):SRQQSRQnextQnext00110110100111QQmemorynot allowedAmirtharajah/Parkhurst, EEC 116 Fall 2011 11Other Latches• Clocked SR latch– Adds clock input. Latch output can only be set/reset when clk=1 (or clk=0)• Other latch types:– JK latch: Removes “not allowed” state – e.g., toggles when inputs are both 1– T latch: Toggles when T input = 1– D latch: Output = D inputAmirtharajah/Parkhurst, EEC 116 Fall 2011 12Latch Circuits• Many methods for implementing latches– Standard CMOS gates (cross-coupled NAND, etc)– Transmission gates– Tri-state invertersAFenentri-state inverterWhen en=0, F is “floating”, i.e. high impedanceAmirtharajah/Parkhurst, EEC 116 Fall 2011 13Positive Dynamic Transmission Gate Latch DQClkClkI0• No feedback devices• Data stored on input capacitance of inverter I0• Dynamic logic issues apply: leakage, capacitive coupling, charge sharing0CAmirtharajah/Parkhurst, EEC 116 Fall 2011 14Transmission Gate Positive Static Latch DQClkClkClkAmirtharajah/Parkhurst, EEC 116 Fall 2011 15Positive Static Latch Timing DiagramDQClkAmirtharajah/Parkhurst, EEC 116 Fall 2011 16NMOS Pass Gate Positive Static Latch DQClkClkTnDDVV−• Fewer devices, less area, lower clock load• Threshold drop on internal nodes implies more static power, less noise marginQAmirtharajah/Parkhurst, EEC 116 Fall 2011 17Master-Slave Flip-Flop• By cascading two level-sensitive latches, one type of edge triggered flip-flop is created• JK latch can be used for first stage so that no input combinations are invalid• SR latch is then used for the second stage because inputs cannot be invalid• Rather than using logic gate-based latches, can cascade latches such as above (e.g., transmission gate dynamic or static latches)Amirtharajah/Parkhurst, EEC 116 Fall 2011 18Edge-Triggered Flip-Flops• Types of latches/flip-flops:– Level-sensitive: output is set when clock is a certain level (0 or 1)– Edge-triggered: output can only be set on a clock edge (rising or falling)• Advantages of edge-triggered flip-flops:– Data only needs to be stable at clock edge– Reduces race conditions: potential errors where an input data change travels through multiple latches during their “transparent” phaseAmirtharajah/Parkhurst, EEC 116 Fall 2011 19“Safest” Edge-Triggered Flip-Flop Master SlaveAmirtharajah/Parkhurst, EEC 116 Fall 2011 20Edge-Triggered Flip-Flop Timing DiagramDQClkAmirtharajah/Parkhurst, EEC 116 Fall 2011 21Dynamic Positive Edge-Triggered FF DQClkClkClkClkI0 I1• No feedback devices• Data stored on input capacitances of inverters I0 and I1• Dynamic logic issues apply: leakage, capacitive coupling, charge sharing0C1CAmirtharajah/Parkhurst, EEC 116 Fall 2011 22Clocked Circuit Timing• Timing definitions:– Clock-to-Q or Propagation Delay (tclkQ): delay of flip-flop from clock edge to output Q–Setup Time (tsetup): amount of time before clock edge that data has to be stable. If data arrives after this time,