EEC 116 Fall 2011 Homework #3Rajeevan AmirtharajahDept. of Electrical and Computer EngineeringUniversity of California, DavisIssued: October 12, 2011Due: October 19, 2011, 4 PM in 2131 Kemper.Reading: Rabaey Chapter 11, 5 [1].Reference: Kang and Leblebici Chapter 5 [2].1 Mirror Adder Delay ParametersFor this problem, consider the mirror adder schematic and transistor aspect ratios as shownin Figure 11-6 on p. 567 of the Rabaey textbook. Assume the units for the widths W in thefigure are microns. Use the following device parameters for the transistors:• NMOS: VT 0= 0.4V, L = 0.8µm, λ = 0.0V−1, µCox= 300µA/V2• PMOS: VT 0= −0.5V, L = 0.8µm, λ = 0.0V−1, µCox= 150µA/V2and assume the power supply voltage VDDis 1.8 V.Problem 1.1 Worst Case Delay Timing Diagram. Draw a timing diagram showinginputs A, B, and Ciand output Cowhich result in the worst case propagation delays tpLHand tpHL.Problem 1.2 Best Case Delay Timing Diagram. Draw a timing diagram showinginputs A, B, and Ciand output Cowhich result in the best case propagation delays tpLHand tpHL.Problem 1.3 Propagation Delay. Calculate the best and worst case low-to-high andhigh-to-low propagation delays (four delay values in total) using the average current method.Assume ideal voltage step inputs and average the current at the beginning and midpoint ofthe transition. Assume the capacitance at Cois 4.8fF.Problem 1.4 Rise and Fall Times. Calculate the best and worst case 10%-90% rise andfall times (four transition time values in total) using the switch RC model. Assume idealvoltage step inputs and that the resistance is fixed from the beginning of the transition.Assume the capacitance at Cois 4.8fF.12 Power Dissipation ComponentsFrequency Ptot10 MHz 101.3µW20 MHz 190.4µW30 MHz 279.5µW40 MHz 368.6µW50 MHz 457.7µW60 MHz 546.8µW70 MHz 635.9µW80 MHz 725.0µW90 MHz 814.1µW100 MHz 903.2µWTable 1: Problem 2 Measured Power Dissipation Values.Table 1 shows measured total power consumption for an integrated circuit versus clockfrequency. Assume the power supply voltage VDD= 1.8V and that direct path (short-circuitcurrent) power Pdp= 0.Problem 2.1 Load Capacitance. Find the load capacitance CLof the integrated circuit.Problem 2.2 Leakage Current. Find the leakage current Ileakfor the integrated circuit.3 Floorplanning and Layout OptimizationFigure 1: Adder cell layout with dimensions.2Figure 1 shows the horizontal and vertical dimensions of a full adder cell which will beused to implement an N bit adder. In this problem, you will find analytical results for theminimum area and perimeter of the adder as a function of its floorplan defined as its aspectratio, i.e. the adder will be laid out in y rows each of which contain x cells. The adderfloorplan is therefore a rectangular array of y rows and x columns.Problem 3.1 Minimum Area. Find the values of x and y which minimize the N bitadder area and derive the minimum area Aminof the adder as a function of Lx, Lyand N .Hint: Use the method of Lagrange multipliers to show that your solution is optimal.Problem 3.2 Minimum Perimeter. Sometimes you are more concerned with minimizingthe perimeter of a design than its area, for example if you want to reduce interference withwiring tracks on different metal layers. Find the values of x and y which minimize the N bitadder perimeter and derive the minimum perimeter Pminof the adder as a function of Lx,Lyand N.References[1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Per-spective, 2nd ed. Upper Saddle River, New Jersey: Prentice-Hall, Inc., 2003.[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,3rd ed. San Francisco: McGraw-Hill, Inc.,